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AD5531BRU 数据表(PDF) 5 Page - Analog Devices |
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AD5531BRU 数据表(HTML) 5 Page - Analog Devices |
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5 / 16 page  REV. 0 AD5530/AD5531 –5– SCLK SYNC SDIN t1 DB15 DB14 DB11 MSB t4 t6 t7 t8 t5 t3 t2 SDO (DAISY CHAINING) RBEN SDO (READBACK) DB15 MSB LSB t14 t15 t16 t17 RB13 RB0 MSB LSB 0 t13 t14 DB0 LSB DB11 DB0 t13 0 Figure 2. Timing Diagram for Daisy-Chaining and READBACK Mode DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS1, 2, 3 Parameter Limit at TMIN, TMAX Unit Description fMAX 2 MHz max SCLK Frequency t1 500 ns min SCLK Cycle Time t2 200 ns min SCLK Low Time t3 200 ns min SCLK High Time t4 50 ns min SYNC to SCLK Falling Edge Setup Time t5 40 ns min SCLK Falling Edge to SYNC Rising Edge t6 50 ns min Min SYNC High Time t7 40 ns min Data Setup Time t8 15 ns min Data Hold Time t12 50 ns min CLR Pulsewidth t13 130 ns min SCLK Falling Edge to SDO Valid t14 50 ns max SCLK Falling Edge to SDO Invalid t15 50 ns min RBEN to SCLK Falling Edge Setup Time t16 50 ns min RBEN Hold Time t17 100 ns min RBEN Falling Edge to SDO Valid 1Guaranteed by design. Not production tested. 2Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2. 3SDO; R PULLUP = 5 k Ω, C L = 15 pF. Specifications subject to change without notice. (VDD = 10.8 V to 16.5 V, VSS = –10.8 V to –16.5 V; VSS = –15 V ±10%; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.) |
类似零件编号 - AD5531BRU |
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类似说明 - AD5531BRU |
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