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A8255 数据表(PDF) 2 Page - Altera Corporation |
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A8255 数据表(HTML) 2 Page - Altera Corporation |
2 / 13 page 46 Altera Corporation a8255 Programmable Peripheral Interface Adapter Data Sheet Table 1 describes the input and output ports of the a8255. Table 1. a8255 Ports Name Type Polarity Description clk Input – Clock. ncs Input Low Chip select. When ncs is asserted, the a8255 is selected and read and write transactions to internal registers are possible. nrd Input Low Read control. When nrd is asserted and the a8255 is selected, read transactions from internal registers are possible. nwr Input Low Write control. When nwr is asserted and the a8255 is selected, write transactions to internal registers are possible. reset Input High Reset. Initializes the control and port C output registers, and sets the port A, B, and C registers to input mode. a[1..0] Input High Register address bus. This bus selects one of the internal registers. din[7..0] Input High Data input bus. The CPU writes data to the internal control, port A, port B, or port C register via the din[7..0] bus. pain[7..0] Input High Port A input data bus. pbin[7..0] Input High Port B input data bus. pcin[7..0] Input High Port C input data bus. paen Output High Port A data enable. Output enable for the port A output data bus. pben Output High Port B data enable. Output enable for the port B output data bus. dout[7..0] Output High Data output bus. The CPU reads data from the internal control, port A, port B, or port C register via the dout[7..0] bus. paout[7..0] Output High Port A output data bus. pbout[7..0] Output High Port B output data bus. pcen[7..0] Output High Port C data enable bus. Output enable for each bit of the port C output data bus. pcout[7..0] Output High Port C output data bus. |
类似零件编号 - A8255 |
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类似说明 - A8255 |
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