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SA24C1024LZEMW 数据表(PDF) 5 Page - List of Unclassifed Manufacturers

部件名 SA24C1024LZEMW
功能描述  1024Kb EEPROM IIC
Download  27 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

SA24C1024LZEMW 数据表(HTML) 5 Page - List of Unclassifed Manufacturers

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SA24C1024 Datasheet
SAIFUN
5
Connection Diagrams
SA24C1024
1
2
3
4
8
7
6
5
NC
A1
NC
V
SS
V
CC
WP
SCL
SDA
SA24C1024
1
2
3
4
8
7
6
5
NC
A1
NC
V
SS
V
CC
SCL
SDA
Figure 2. SO Package (MW), Dual Inline (N) – Top
View
Figure 3. Leadless Package (MLF) – Top View
Note:
For more details, refer to package number N08E and M08D.
Table 1. Pin Names
Symbol
Pin Name
Description
NC
Not Connected
A1
Device Select Address Input
Pin
Has an internal "weak" pulldown, and assumes logic LOW
when left unconnected.
NC
Not Connected
VSS
Device Ground Input Pin
SDA
IIC Data Input/Output Pin
Open Collector/Drain type.
SCL
IIC Clock Input Pin
WP
Write Protect
Has an internal "weak" pulldown, and assumes logic LOW
when left unconnected.
When LOW, writing is allowed to the memory array.
When HIGH, writing is not allowed to the memory array, as
defined in Write Protect (WP), page 14.
VCC
Device Power Input Pin
2.7 V to 3.6 V
Note:
No A2 or A0 pins (Pins 2 and 3) are provided, and are instead treated as Not
Connected. Internal address comparison assumes pin A2 to be 0, and so the
command code should have its corresponding A2 bit set to 0 as well. The
command code should also have its corresponding A0 bit set to add16 (MSB
address bit).


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