11

Application Information

Bypassing and PC Board Layout

The HCPL-7723/0723 optocouplers are extremely easy to

use. No external interface circuitry is required because

the HCPL-7723/0723 use high-speed CMOS IC technol-

ogy allowing CMOS logic to be connected directly to the

inputs and outputs.

As shown in Figure 7, the only external components

required for proper operation are two bypass capacitors.

Capacitor values should be between 0.01 µF and 0.1 µF.

For each capacitor, the total lead length between both

ends of the capacitor and the power-supply pins should

not exceed 20 mm. Figure 8 illustrates the recommended

printed circuit board layout for the HCPL-7723/0723.

Figure 9. Timing diagram to illustrate propagation delay, tplh and tphl.

INPUT

tPLH

tPHL

OUTPUT

VI

VO

10%

90%

90%

10%

VOH

VOL

0 V

50%

5 V CMOS

2.5 V CMOS

Figure 7. Functional diagram.

Figure 8. Recommended printed circuit board layout.

Propagation Delay, Pulse-Width Distortion and Propa-

gation Delay Skew

Propagation Delay is a figure of merit which describes

how quickly a logic signal propagates through a system

as illustrated in Figure 9. The propagation delay from low

signal to propagate to the output, causing the output to

change from low to high. Similarly, the propagation delay

the input signal to propagate to the output, causing the

output to change from high to low.

7

5

6

8

2

3

4

1

GND2

C1

C2

NC

VDD2

NC

VO

VDD1

VI

C1, C2 = 0.01 µF TO 0.1 µF

GND1

C1

C2

C1, C2 = 0.01 µF TO 0.1 µF