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AD4001BCPZ-RL7 数据表(PDF) 6 Page - Analog Devices |
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AD4001BCPZ-RL7 数据表(HTML) 6 Page - Analog Devices |
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6 / 34 page  Data Sheet AD4001 Rev. 0 | Page 5 of 33 Parameter Test Conditions/Comments Min Typ Max Unit TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +125 °C 1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS. 2 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 3 Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. 4 The minimum and maximum values are guaranteed by characterization, not production tested. 5 See the 1/f noise plot in Figure 18. TIMING SPECIFICATIONS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, and turbo mode enabled (fS = 2 MSPS), unless otherwise noted. See Figure 2 for the timing voltage levels. Table 2. Digital Interface Timing Parameter Symbol Min Typ Max Unit Conversion Time—CNV Rising Edge to Data Available tCONV 290 320 ns Acquisition Phase1 tACQ 290 ns Time Between Conversions tCYC 500 ns CNV Pulse Width (CS Mode)2 tCNVH 10 ns SCK Period (CS Mode)3 tSCK VIO > 2.7 V 9.8 ns VIO > 1.7 V 12.3 ns SCK Period (Daisy-Chain Mode)4 tSCK VIO >2.7 V 20 ns VIO > 1.7 V 25 ns SCK Low Time tSCKL 3 ns SCK High Time tSCKH 3 ns SCK Falling Edge to Data Remains Valid Delay tHSDO 1.5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO > 2.7 V 7.5 ns VIO > 1.7 V 10.5 ns CNV or SDI Low to SDO D15 Most Significant Bit (MSB) Valid Delay (CS Mode) tEN VIO > 2.7 V 10 ns VIO > 1.7 V 13 ns CNV Rising Edge to First SCK Rising Edge Delay tQUIET1 190 ns Last SCK Falling Edge to CNV Rising Edge Delay5 tQUIET2 60 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 20 ns SDI Valid Setup Time from CNV Rising Edge tSSDICNV 2 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 2 ns SCK Valid Hold Time from CNV Rising Edge (Daisy-Chain Mode) tHSCKCNV 12 ns SDI Valid Setup Time from SCK Rising Edge (Daisy-Chain Mode) tSSDISCK 2 ns SDI Valid Hold Time from SCK Rising Edge (Daisy-Chain Mode) tHSDISCK 2 ns 1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS. 2 For turbo mode, tCNVH must match the tQUIET1 minimum. 3 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. 4 A 50% duty cycle is assumed for SCK. 5 See Figure 22 for SINAD vs. tQUIET2. X% VIO1 Y% VIO1 VIH2 VIL2 VIL2 VIH2 tDELAY tDELAY 1FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30. 2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 1. Figure 2. Voltage Levels for Timing |
类似零件编号 - AD4001BCPZ-RL7 |
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类似说明 - AD4001BCPZ-RL7 |
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