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CS7808-CM 数据表(PDF) 8 Page - Cirrus Logic |
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CS7808-CM 数据表(HTML) 8 Page - Cirrus Logic |
8 / 52 page CS7808 8 1.2.2 SDRAM Interface CS7808 interfaces with either SDRAM or SGRAM for high data bandwidth transfer. Figure 2 shows the refresh cycle performed by CS7808. Figure 3 shows a burst write (length = 8) transaction. Figure 4 on page 9 shows a burst read (length = 8) transaction, while Figure 5 on page 9 shows detailed SDRAM in- terface timing. In both Figure 3 and Figure 4,CAS latencyis programmedto3. Symbol Description Min Typ Max Unit tmsur M_D[31:0] setup to M_CKO 3 ns tmhr M_D[31:0] hold time after M_CKO 0 ns tmco M_CKO active edge to Output transition 7 ns tmper M_CKO Period1 1.Values are guaranteed by design only. 10.5 12.2 ns tmhw M_D[31:0] valid time after M_CKO 5 ns tmdow M_D[31:0] delay from M_CKO rising edge 5 ns Table 2. SDRAM Interface Characteristics M_CKE M_A_[11:0] M_BS_N M_RAS_N M_CAS_N M_WE_N MD[31:0] M_DQM_[3:0] M_AP Figure 2. SDRAM Refresh Transaction D0 D1 D2 D3 D4 D5 D6 D7 C1 C2 C3 C4 C5 C6 C7 C0 R0 M_CKO M_A_[11:0] M_BS_N M_RAS_N M_CAS_N M_WE_N M_D_[31:0] M_DQM_[3:0] M_AP Figure 3. SDRAM Burst Write Transaction |
类似零件编号 - CS7808-CM |
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类似说明 - CS7808-CM |
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