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STK14CA8-R35I 数据表(PDF) 5 Page - List of Unclassifed Manufacturers |
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STK14CA8-R35I 数据表(HTML) 5 Page - List of Unclassifed Manufacturers |
5 / 15 page STK14CA8 December 2004 Document Control #ML0022 rev 1.0 5 SRAM READ CYCLES #1 & #2 SYMBOLS STK14CA8-25 STK14CA8-35 STK14CA8-45 NO. #1 #2 Alt. PARAMETER MIN MAX MIN MAX MIN MAX UNITS 1 tELQV tACS Chip Enable Access Time 25 35 45 ns 2 tAVAV c tAVAV c tRC Read Cycle Time 25 35 45 ns 3 tAVQV d tAA Address Access Time 25 35 45 ns 4 tGLQV tOE Output Enable to Data Valid 12 15 20 ns 5 tAXQX d tOH Output Hold after Address Change 3 3 3 ns 6 tELQX tLZ Chip Enable to Output Active 3 3 3 ns 7 tEHQZ e tHZ Chip Disable to Output Inactive 10 13 15 ns 8 tGLQX tOLZ Output Enable to Output Active 0 0 0 ns 9 tGHQZ e tOHZ Output Disable to Output Inactive 10 13 15 ns 10 tELICC b tPA Chip Enable to Power Active 0 0 0 ns 11 tEHICC b tPS Chip Disable to Power Standby 25 35 45 ns Notes c: W must be high during SRAM READ cycles d: Device is continuously selected with E and G both low e: Measured ± 200mV from steady state output voltage f: HSB must remain high during READ and WRITE cycles. SRAM READ CYCLE #1: Address Controlledc,d,f SRAM READ CYCLE #2: E Controlledc,f DQ (DATA OUT) ADDRESS 3 tAVQV 5 tAXQX DATA VALID 2 tAVAV 2 tAVAV DATA VALID ADDRESS DQ (DATA OUT) ICC STANDBY ACTIVE 1 tELQV 6 tELQX 4 tGLQV 8 tGLQX 10 tELICCH 11 tEHICCL 7 tEHQZ 9 tGHQZ E G |
类似零件编号 - STK14CA8-R35I |
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类似说明 - STK14CA8-R35I |
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