CS4122

http://onsemi.com

7

Input Code

(Decimal)

Ideal

Degrees

Nominal

Degrees

(V)

(V)

0

0

0.176

0.032

10.472

128

45

45.176

10.472

10.412

256

90

90.176

10.472

−0.032

384

135

135.176

10.412

−10.472

512

180

180.176

−0.032

−10.472

640

225

225.176

−10.472

−10.412

768

270

270.176

−10.472

0.032

896

315

315.176

−10.476

10.412

1023

359.65

359.826

−0.032

10.472

Input Code

(Decimal)

Scale

Degrees

Degrees

from Center

0

0

−56.1

10.417

127

55.88

−0.22

0.027

128

56.32

0.22

−0.027

255

112.2

56.1

−10.417

The 12 bits are shifted into the device’s shift register MSB

first using a SPI compatible scheme. This method is shown

in Figures 6 and 7. The first 2 bits select the output driver for

which the data is intended. The CS must be high and remain

high for SCLK to be enabled. Data on SI is shifted in on the

rising edge of the synchronous clock signal. Data in the shift

register is shifted to SO on the falling edge of SCLK. This

arrangement allows the cascading of devices. SO is always

enabled. Data shifts through without affecting the outputs

until CS is brought low. At this time, the internal DAC is

updated and the outputs change accordingly.

CS

SI

SCLK

SO

10% − 90%

Figure 7. Serial Data Timing Diagram

The DAC for the major gauge driver outputs 128 discrete

levels selected by bits D6 − D0. These bits are XOR’d with

D7 to invert them when choosing the 2nd half of each

quadrant (each odd octant). This reduces the number of

resistors and switches required. The MUX chooses which

signals to send to the output amplifiers based upon D9 − D7.

There are three choices for each amplifier: high, low or the

DAC output.

The DAC’s for the minor gauge drivers similarly output

128 discrete levels selected by bits D6 − D0. These bits are

also XOR’d with D7 to invert them when choosing the 2nd

half of the output range. The MUX chooses which signals to

send to the output amplifiers based upon D7. There are two

choices for each amplifier; high or the DAC output. Bits D8

and D9 are not used, but should be set to “00” to ensure that

the minor gauge outputs are enabled.

The output buffers are unity gain amplifiers. Each of the

eight outputs are designed to swing close to the supply rails

to maximize the voltage across the coils to produce

maximum torque. Additionally, this lowers the power

dissipation. The current for each output is also monitored. If

any of the major gauge outputs exceed the maximum value,

all of the major outputs are disabled. If any of the minor

gauge outputs exceed the maximum value, all of the minor

outputs are disabled. The falling edge of the CS re−enables

the outputs with the fault condition but they remain on only

if the overcurrent situation has been eliminated.