数据搜索系统,热门电子元器件搜索
  Chinese  ▼

Delete All
ON OFF
ALLDATASHEETCN.COM

X  

预览 PDF Download HTML

HS-82C37 数据表(PDF) 23 Page - Harris Corporation

部件名 HS-82C37
功能描述  Radiation Hardened CMOS High Performance Programmable DMA Controller
Download  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  HARRIS [Harris Corporation]
网页  http://www.harris.com
标志 HARRIS - Harris Corporation

HS-82C37 数据表(HTML) 23 Page - Harris Corporation

Back Button HS-82C37 Datasheet HTML 19Page - Harris Corporation HS-82C37 Datasheet HTML 20Page - Harris Corporation HS-82C37 Datasheet HTML 21Page - Harris Corporation HS-82C37 Datasheet HTML 22Page - Harris Corporation HS-82C37 Datasheet HTML 23Page - Harris Corporation HS-82C37 Datasheet HTML 24Page - Harris Corporation HS-82C37 Datasheet HTML 25Page - Harris Corporation HS-82C37 Datasheet HTML 26Page - Harris Corporation HS-82C37 Datasheet HTML 27Page - Harris Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 23 / 28 page
background image
23
HS-82C37ARH
Mask Register - Each channel has associated with it a
mask bit which can be set to disable an incoming DREQ.
Each mask bit is set when its associated channel produces
an EOP if the channel is not programmed to Autoinitialize.
Each bit of the 4-bit Mask Register may also be set or
cleared separately or simultaneously under soft-ware con-
trol. The entire register is also set by a Reset or Master
Clear. This disables all hardware DMA requests until a clear
Mask Register instruction allows them to occur. The instruc-
tion to separately set or clear the mask bits is similar in form
to that used with the Request Register. Refer to the following
table and Figure 10 for details. When reading the Mask Reg-
ister, bits 4-7 will always read as logical ones, and bits 0-3
will display the mask bits of channel 0-3, respectively. The 4
bits of the Mask Register may be cleared simultaneously by
using the Clear Mask Register command (see software com-
mands section).
Mask Register
All four bits of the Mask Register may also be written with a
single command.
76543210
00
01
10
11
0
1
BIT NUMBER
SELECT CHANNEL 0 MASK BIT
SELECT CHANNEL 1 MASK BIT
SELECT CHANNEL 2 MASK BIT
SELECT CHANNEL 3 MASK BIT
CLEAR MASK BIT
SET MASK BIT
DON’T CARE
76543210
0
1
0
1
0
1
BIT NUMBER
CLEAR CHANNEL 0 MASK BIT
SET CHANNEL 0 MASK BIT
CLEAR CHANNEL 1 MASK BIT
SET CHANNEL 1 MASK BIT
CLEAR CHANNEL 2 MASK BIT
SET CHANNEL 2 MASK BIT
DON’T CARE,
WRITE ALL
ONES,
READ
0
1
CLEAR CHANNEL 3 MASK BIT
SET CHANNEL 3 MASK BIT
Mode Register - Each channel has a 6-bit Mode Register
associated with it. When the register is being written to by
the microprocessor in the Program Condition, bits 0 and 1
determine which channel Mode Register is to be written.
When the processor reads a Mode Register, bits 0 and 1 will
both be ones. See the adjacent table and Figure 10 for Mode
Register functions and addresses.
Mode Register
Request Register - The HS-82C37ARH can respond to
requests for DMA service which are initiated by software as
well as by a DREQ. Each channel has a request bit associ-
ated with it in the 4-bit Request Register. These are non-
maskable and subject to prioritization by the Priority Encoder
network. Each register bit is set or reset separately under
software control. The entire register is cleared by a Reset. To
set or reset a bit, the software loads the proper form of the
data word. See Figure 10 for register address coding, and
the following table for Request Register format. A software
request for DMA operation can be made in Block or Single
Modes. For Memory-to-Memory transfers, the software
request for channel 0 should be set. When reading the
Request Register, bits 4-7 will always read as ones, and bits
0-3 will display the request bits of channels 0-3 respectively.
Request Register
76543210
00
01
10
11
BIT NUMBER
CHANNEL 0 SELECT
CHANNEL 1 SELECTT
CHANNEL 2 SELECT
CHANNEL 3 SELECT
00
01
10
11
VERIFY TRANSFER
WRITE TRANSFER
READ TRANSFER
ILLEGAL
0
1
AUTOINITIALIZATION DISABLE
AUTOINITIALIZATION ENABLE
00
01
10
11
DEMAND MODE SELECT
SINGLE MODE SELECT
BLOCK MODE SELECT
CASCADE MODE SELECT
0
1
ADDRESS INCREMENT SELECT
ADDRESS DECREMENT SELECT
XX READBACK
XX IF BITS 6 AND 7 = 11
76543210
00
01
10
11
0
1
BIT NUMBER
SELECT CHANNEL 0
SELECT CHANNEL 1
SELECT CHANNEL 2
SELECT CHANNEL 3
RESET REQUEST BIT
SET REQUEST BIT
DON’T CARE,
WRITE BITS 4-7
ALL ONES, READ
Spec Number
518058


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28 


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn