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TSC2100IDAR 数据表(PDF) 10 Page - Texas Instruments |
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TSC2100IDAR 数据表(HTML) 10 Page - Texas Instruments |
10 / 71 page TSC2100 SLAS378− NOVEMBER 2003 www.ti.com 10 LRCK/ADWS BCLK DOUT DIN tL(BCLK) ts (DI) th (DI) th (WS) tS (WS) tH(BCLK) td(DO−BCLK) td(DO−WS) tP(BCLK) Figure 3. I2S/LJF/RJF Timing in Slave Mode TYPICAL TIMING REQUIREMENTS (FIGURE 3) All specifications at 25 °C, DVDD = 1.8 V (1) PARAMETER IOVDD = 1.1 V IOVDD = 3.3 V UNITS PARAMETER MIN MAX MIN MAX UNITS tH (BCLK) BCLK high period 35 35 ns tL (BCLK) BCLK low period 35 35 ns ts(WS) ADWS/LRCK setup 6 6 ns th(WS) ADWS/LRCK hold 6 6 ns td (DO−WS) ADWS to DOUT delay (for LJF mode) 25 18 ns td (DO−BCLK) BCLK to DOUT delay 25 15 ns ts(DI) DIN setup 6 6 ns th(DI) DIN hold 6 6 ns tr Rise time 5 4 ns tf Fall time 5 4 ns (1) These parameters are based on characterization and are not tested in production. |
类似零件编号 - TSC2100IDAR |
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类似说明 - TSC2100IDAR |
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