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ST16C2550CQ48 数据表(PDF) 4 Page - Exar Corporation

部件名 ST16C2550CQ48
功能描述  DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFOS
Download  34 Pages
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制造商  EXAR [Exar Corporation]
网页  http://www.exar.com
标志 EXAR - Exar Corporation

ST16C2550CQ48 数据表(HTML) 4 Page - Exar Corporation

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ST16C2550
4
Rev. 3.20
SYMBOL DESCRIPTION
Symbol
Pin
Signal
Pin Description
40
44
48
type
A0
28
31
28
I
Address-0 Select Bit. - Internal register address selection.
A1
27
30
27
I
Address-1 Select Bit. - Internal register address selection.
A2
26
29
26
I
Address-2 Select Bit. - Internal register address selection.
-CS A-B
14,15 16,17 10,11
I
Chip Select A, B (active low) - This function is associated
with individual channels, A through B. These pins enable
data transfers between the user CPU and the 2550 for the
channel(s) addressed. Individual UART sections (A, B) are
addressed by providing a logic 0 on the respective -CS A-
B pin.
D0-D7
1-8
2-9
44-48
I/O
1-3
Data Bus (Bi-directional) - These pins are the eight bit, three
state data bus for transferring information to or from the
controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
GND
20
22
17
Pwr
Signal and power ground.
INT A-B
30,29 33,32 30,29
O
Interrupt A, B (three state) - This function is associated with
individual channel interrupts, INT A-B. INT A-B are enabled
when MCR bit-3 is set to a logic 1, interrupts are enabled in
the interrupt enable register (IER), and when an interrupt
condition exists. Interrupt conditions include: receiver er-
rors, available receiver buffer data, transmit buffer empty,
or when a modem status flag is detected.
-IOR
21
24
19
I
Read strobe. (active low Strobe) - A logic 0 transition on this
pin will load the contents of an Internal register defined by
address bits A0-A2 onto the 2550 data bus (D0-D7) for
access by an external CPU.
-IOW
18
20
15
I
Write strobe. (active low strobe) - A logic 0 transition on this
pin will transfer the contents of the data bus (D0-D7) from
the external CPU to an internal register that is defined by
address bits A0-A2.
-OP2 A-B
31,13 35,15
32,9
O
Output -2 (User Defined). - This function is associated with


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