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AD8251 数据表(PDF) 5 Page - Analog Devices

部件名 AD8251
功能描述  Devices Connected
Download  13 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD8251 数据表(HTML) 5 Page - Analog Devices

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Circuit Note
CN-0385
Rev. 0 | Page 5 of 13
Table 2. Noise Performance for the Multichannel Data Acquisition System
ADG5207
AD8251
AD8475
AD4003
Total
Gain
en, ADG5207
(nV/√Hz)
vn, ADG5207
(µV rms)
en, AD8251
(nV/√Hz)
vn, AD8251
(µV rms)
en, AD8475
(nV/√Hz)
vn, AD8475
(µV rms)
vn, AD4003
(µV rms)
vn, total
(µV rms)
SNR
(dB)
0.4
2.04
2.29
40
44.7
10
28
35.4
63.6
93.2
0.8
2.04
4.57
27
60.4
10
28
35.4
75.5
91.7
1.6
2.04
9.15
22
98.4
10
28
35.4
108.6
88.5
3.2
2.04
18.3
18
161
10
28
35.4
168.2
84.7
Settling Time Analysis
When the circuit shown in Figure 1 is sampling multiple
channels, each of the different inputs are merged into a time-
division multiplexed signal by the ADG5207. Multiplexed
signals are discontinuous in nature, and typically have large
voltage steps occurring in short time intervals. For the system
in Figure 1, the voltage differential between two consecutive
channels may be as large as 20 V at the inputs of the ADG5207,
and the time allotted for settling is only as long as the sampling
period.
Figure 3 shows the settling time model of the circuit in Figure 1.
Each of the components in the system has its own settling
characteristics (see the following sections).
Figure 3. Settling Time Model of CN-0385 Circuit
Settling time is defined as the time required for the analog front-
end circuitry to settle an input step to a certain precision. This
precision is usually specified in percent error (for example, 0.1%
or 0.01%); however, in conversion systems, it is also helpful to
relate it to resolution. For example, settling to a 16-bit resolution
is roughly equivalent to settling to 0.001%. Table 3 shows the
relationship between settling to percent error and to resolution
for a single-pole system.
Table 3. Percent Error and Effective Resolution
Resolution,
No. of Bits
LSB (%FS)
No. of Time Constants =
−ln (% Error/100)
6
1.563
4.16
8
0.391
5.55
10
0.0977
6.93
12
0.0244
8.32
14
0.0061
9.70
16
0.00153
11.09
18
0.00038
12.48
20
0.000095
13.86
22
0.000024
15.25
Estimating the settling time of an analog front end with
multiple components is not trivial for a variety of reasons. First,
many devices do not specify settling characteristics to very high
precision. Settling time for an active device is also not linearly
related to settling precision, and it may take up to 30 times as
long to settle to 0.01% as to 0.1%. The settling time can be due
to long-term thermal effects inside the amplifier. Settling time
is also dependent on the load that the device is driving, and
settling time is generally not characterized for multiple load
conditions.
Measuring high precision settling is also difficult without a
specialized characterization platform, because of the effects of
oscilloscope overdrive and sensitivity, and the difficulty of
generating an input pulse with sufficient rise time and settling
time.
Settling time can be estimated provided certain bounds and
assumptions are used in analyzing the circuit. The total settling
time can be calculated by taking the rss of the settling times of
the individual components:
2
S_AD4003
2
S_AD8475
2
S_AD8251
2
S_ADG5207
_
t
t
t
t
t TOTAL
S
+
+
+
=
The maximum throughput of the system is inversely proportional
to the total settling time:
TOTAL
S
SR
t
f
_
1
<
Settling Time of the ADG5207
The equivalent circuit for a CMOS switch can be approximated as
an ideal switch in series with a resistor (RON) and in parallel with
two capacitors (CS, CD). The multiplexer stage and associated
filters can therefore be modeled as shown in Figure 4.
Figure 4. Settling Time Model of the ADG5207
PART 3
ADC DRIVER
AD8475
tS_ADG5207
tS_AD8251
tS_AD8475
RC + MUX
ADG5207
PART 4
RC + ADC
AD4003
tS_AD4003
PART 2
PART 1
PGIA
AD8251
CIN
ADG5207
RON
RON
RON
RON
RS
RS
CIN
CD
CD
CS
CS
CS
CS
AD8251
S1A
S8A
DA
S1B
S8B
DB


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