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ADP7182ACPZ-5.0-R7 数据表(PDF) 21 Page - Analog Devices |
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ADP7182ACPZ-5.0-R7 数据表(HTML) 21 Page - Analog Devices |
21 / 31 page Data Sheet ADP7182 Rev. I | Page 21 of 31 THEORY OF OPERATION The ADP7182 is a low quiescent current, LDO linear regulator that operates from −2.7 V to −28 V and can provide up to −200 mA of output current. Drawing a low −650 μA of quiescent current (typical) at full load makes the ADP7182 ideal for battery-powered portable equipment. Maximum shutdown current consumption is −8 μA at room temperature. Optimized for use with small 2.2 μF ceramic capacitors, the ADP7182 provides excellent transient performance. VOUT GND EN VIN REFERENCE SHUTDOWN SHORT CIRCUIT THERMAL PROTECT VREG Figure 77. Fixed Output Voltage Internal Block Diagram VOUT ADJ GND EN VIN –1.22V REFERENCE SHUTDOWN SHORT CIRCUIT THERMAL PROTECT VREG Figure 78. Adjustable Output Voltage Internal Block Diagram Internally, the ADP7182 consists of a reference, an error amplifier, a feedback voltage divider, and an NMOS pass transistor. Output current is delivered via the NMOS pass transistor, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is more positive than the reference voltage, the gate of the NMOS transistor is pulled toward GND, allowing more current to pass and increasing the output voltage. If the feedback voltage is more negative than the reference voltage, the gate of the NMOS transistor is pulled toward −VIN, allowing less current to pass and decreasing the output voltage. The ESD protection devices are shown in the block diagram as Zener diodes (see Figure 77 and Figure 78). ADJUSTABLE MODE OPERATION The ADP7182 is available in a fixed output voltage and an adjustable mode version with an output voltage that can be set to between −1.22 V and −27 V by an external voltage divider. The output voltage can be set according to −VOUT = −1.22 V (1 + RFB1/RFB2) RFB2 must be less than 120 kΩ to minimize the output voltage errors due to the leakage current of the ADJ pin. The error voltage caused by the ADJ pin leakage current is the parallel combination of RFB1 and RFB2 times the ADJ pin leakage current. For example, when RFB1 = RFB2 = 120 kΩ, the output voltage is −2.44 V and the error due to the typical ADJ pin leakage current (10 nA) is 60 kΩ times 10 nA, or 6 mV. This example results in an output voltage error of 0.245%. The addition of a small capacitor (~100 pF) in parallel with RFB1 can improve the stability of the ADP7182. Larger values of capacitance also reduce the noise and improve PSRR (see the Noise Reduction of the Adjustable section). RFB2 120kΩ RFB1 120kΩ GND EN ADJ VIN VOUT ADP7182 ON ON –2V OFF 0V 2V VIN = –3V VOUT = –2.44V COUT 2.2µF CIN 2.2µF Figure 79. Setting Adjustable Output Voltage |
类似零件编号 - ADP7182ACPZ-5.0-R7 |
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类似说明 - ADP7182ACPZ-5.0-R7 |
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