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AD9528BCPZ-REEL7 数据表(PDF) 6 Page - Analog Devices |
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AD9528BCPZ-REEL7 数据表(HTML) 6 Page - Analog Devices |
6 / 68 page Data Sheet AD9528 Rev. C | Page 5 of 67 Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY CURRENT FOR EACH CLOCK DISTRIBUTION CHANNEL Each clock output channel has a dedicated VDD pin. The current draw for each VDD pin includes the divider, fine delay, and output driver, fine delay is off; see the Pin Configuration and Function Descriptions section for pin assignment LVDS Mode, 3.5 mA 21 23 mA Output = 122.88 MHz, channel divider = 10 24 26 mA Output = 409.6 MHz, channel divider = 3 28 30 mA Output = 737.28 MHz, channel divider = 1, VCO divider = 5, LVDS boost mode of 4.5 mA recommended LVDS Boost Mode, 4.5 mA 22 24 mA Output = 122.88 MHz, channel divider =10 25 27 mA Output = 409.6 MHz, channel divider = 3 29 31 mA Output = 737.28 MHz, channel divider = 1, VCO divider = 5 HSTL Mode, 9 mA 25 27 mA Output = 122.88 MHz, channel divider =10 26 28 mA Output = 409.6 MHz, channel divider = 3 29 31 mA Output = 983.04 MHz, channel divider = 1, VCO divider = 5, VCO = 3932.16 MHz 37 41 mA Output = 1228.8 MHz, channel divider = 1, only output channels OUT1 and OUT2 support output frequencies greater than ~1 GHz Chip Power-Down Mode 2.5 4 mA For each channel VDD pin, chip power-down bit enabled (Register 0x0500, Bit 0 = 1) POWER DISSIPATION Table 3. Parameter Min Typ Max Unit Test Conditions/Comments TOTAL POWER DISSIPATION Does not include power dissipated in termination resistors Typical Dual Loop Mode Configuration 1675 1780 mW Differential REFA input at 122.88 MHz; f VCXO = 122.88 MHz, fVCO = 3686.4 MHz, VCO divider at 3 clock distribution outputs running as follows: 7 HSTL at 122.88 MHz, 7 LVDS (3.5 mA) at 960 kHz Typical Single Loop Mode Configuration 1635 1810 mW PLL1 off, differential VCXO input at 122.88 MHz, clock distribution outputs running as follows: 7 HSTL at 122.88 MHz, 7 LVDS (3.5 mA) at 960 kHz Typical Buffer Mode 1030 1200 mW PLL1 and PLL2 off, differential VCXO input at 122.88 MHz. SYSREF generator off, differential SYSREF input at 960 kHz; clock distribution outputs running as follows: 7 HSTL at 122.88 MHz, 7 LVDS (3.5 mA) at 960 kHz Chip Power-Down Mode 65 mW Chip power-down bit enabled (Register 0x0500, Bit 0 = 1) RESET Enabled 1015 1200 mW RESET pin low INCREMENTAL POWER DISSIPATION Does not include power dissipated in termination resistors Low Power Base Configuration 590 mW Dual loop mode, SYSREF generation and fine delay off; total power with 1 LVDS output running at 122.88 MHz, single-ended REFA at 122.88 MHz; REFB off, VCXO = 122.88 MHz, VCO = 3686.4 MHz PLL1 OFF 0 mW Define settings to power off PLL1 Output Distribution Incremental power increase for each additional enable output LVDS Mode, 3.5 mA 70 mW Single 3.5 mA LVDS output at 122.88 MHz, channel divider = 10 78 mW Single 3.5 mA LVDS output at 409.6 MHz, channel divider = 3 92 mW Single 3.5 mA LVDS output at 737.28 MHz, VCO divider = 5, channel divider = 1 LVDS Mode, 4.5 mA 73 mW Single 4.5 mA LVDS output at 122.88 MHz, channel divider = 10 81 mW Single 4.5 mA LVDS output at 409.6 MHz, channel divider = 3 95 mW Single 4.5 mA LVDS output at 737.28 MHz, VCO divider = 5 |
类似零件编号 - AD9528BCPZ-REEL7 |
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类似说明 - AD9528BCPZ-REEL7 |
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