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ADRF6820 数据表(PDF) 1 Page - Analog Devices |
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ADRF6820 数据表(HTML) 1 Page - Analog Devices |
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1 / 45 page  695 MHz to 2700 MHz, Quadrature Demodulator with Integrated Fractional-N PLL and VCO Data Sheet ADRF6820 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES I/Q demodulator with integrated fractional-N PLL RF input frequency range: 695 MHz to 2700 MHz Internal LO frequency range: 356.25 MHz to 2850 MHz Input P1dB: 14.5 dBm at 1900 MHz RF Input IP3: 35 dBm at 1900 MHz RF Programmable HD3/IP3 trim Single pole, double throw (SPDT) RF input switch RF digital step attenuation range: 0 dB to 15 dB Integrated RF tunable balun for single-ended 50 Ω input Multicore integrated VCO Demodulated 1 dB bandwidth: 600 MHz Demodulated 3 dB bandwidth: 1400 MHz 4 selectable baseband gain and bandwidth modes Digital programmable LO phase offset and dc nulling Programmable via 3-wire serial port interface (SPI) 40-lead, 6 mm × 6 mm LFCSP APPLICATIONS Cellular W-CDMA/GSM/LTE Digital predistortion (DPD) receivers Microwave point-to-point radios FUNCTIONAL BLOCK DIAGRAM DC/PHASE CORRECTION DC/PHASE CORRECTION SERIAL PORT INTERFACE 15 14 13 24 2 3 8 9 23 25 26 28 38 VPOS_3P3 DECL1 TO DECL4 21 11 19 30 31 36 27 33 40 10 1 VPOS_5V LDO VCO LDO 2.5V RFIN0 RFIN1 29 22 POLYPHASE FILTER LOIN– REFIN LOIN+ I+ I– Q– Q+ QUAD DIVIDER PLL 34 39 35 5 4 7 6 Figure 1. GENERAL DESCRIPTION The ADRF6820 is a highly integrated demodulator and synthesizer ideally suited for next generation communication systems. The feature rich device consists of a high linearity broadband I/Q demodulator, an integrated fractional-N phase-locked loop (PLL), and a low phase noise multicore, voltage controlled oscillator (VCO). The ADRF6820 also integrates a 2:1 RF switch, an on-chip tunable RF balun, a programmable RF attenuator, and two low dropout (LDO) regulators. This highly integrated device fits within a small 6 mm × 6 mm footprint. The high isolation 2:1 RF switch and on-chip tunable RF balun enable the ADRF6820 to support two single-ended, 50 Ω terminated RF inputs. A programmable attenuator ensures an optimal differential RF input level to the high linearity demodulator core. The integrated attenuator offers an attenuation range of 0 dB to 15 dB with a step size of 1 dB. The ADRF6820 offers two alternatives for generating the differential local oscillator (LO) input signal: externally via a high frequency, low phase noise LO signal or internally via the on-chip fractional-N synthesizer. The integrated synthesizer enables continuous LO coverage from 356.25 MHz to 2850 MHz. The PLL reference input can support a wide frequency range because the divide or multiplication blocks can increase or decrease the reference frequency to the desired value before it is passed to the phase frequency detector (PFD). When selected, the output of the internal fractional-N synthesizer is applied to a divide-by-2 quadrature phase splitter. From the external LO path, a 1× LO signal can be applied to the built-in polyphase filter, or a 2× LO signal can be used with the divide- by-2 quadrature phase splitter to generate the quadrature LO inputs to the mixers. The ADRF6820 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, RoHS-compliant, 6 mm × 6 mm LFCSP package with an exposed paddle. Performance is specified over the −40°C to +85°C temperature range. |
类似零件编号 - ADRF6820 |
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类似说明 - ADRF6820 |
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