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ADP7183ACPZN3.3-R7 数据表(PDF) 6 Page - Analog Devices |
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ADP7183ACPZN3.3-R7 数据表(HTML) 6 Page - Analog Devices |
6 / 19 page ADP7183 Data Sheet Rev. 0 | Page 6 of 19 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 3 VA 4 VAFB 1 VOUT 2 SENSE 6GND 5EN 8VIN 7VREG ADP7183 TOP VIEW (Not to Scale) NOTES 1. EXPOSED PAD. THE EXPOSED PAD ENHANCES THE THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO VIN INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD CONNECT TO THE INPUT VOLTAGE PLANE ON THE BOARD. Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 VOUT Regulated Output Voltage. Bypass the VOUT pin to the GND pin with a 4.7 μF or greater capacitor. 2 SENSE Sense Input. Connect this pin to the VOUT pin. 3 VA Low Noise Reference Voltage. Connect a 1 μF capacitor to GND to reduce noise. Do not connect a load to ground. 4 VAFB Output Voltage Reference Feedback (Adjust Mode). Connect a 1 nF to 1 μF capacitor between the VAFB pin and the VA pin to reduce noise. Start-up time is increased as a function of the capacitance. Connect an external resistor divider between the VA pin and the VAFB pin to set the output voltage in adjust mode. 5 EN Enable. Drive EN at least +1.25 V above or −1.3 V below ground to enable the regulator or drive EN to ground to turn the regulator off. For automatic startup, connect EN to VIN. 6 GND Ground. 7 VREG Regulated Input Supply to the LDO Amplifier. Bypass VREG to GND with a 1 μF or greater capacitor. Do not connect a load to ground. 8 VIN Regulator Input Supply. Bypass VIN to GND with a 4.7 μF or greater capacitor. EP Exposed Pad. The exposed pad enhances the thermal performance and is electrically connected to VIN inside the package. It is recommended that the exposed pad connect to the input voltage plane on the board. |
类似零件编号 - ADP7183ACPZN3.3-R7 |
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类似说明 - ADP7183ACPZN3.3-R7 |
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