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ADF4355-3BCPZ 数据表(PDF) 9 Page - Analog Devices |
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ADF4355-3BCPZ 数据表(HTML) 9 Page - Analog Devices |
9 / 35 page ADF4355-3 Data Sheet Rev. A | Page 8 of 34 Pin No. Mnemonic Description 22 RSET Bias Current Resistor. Connecting a resistor between this pin and ground sets the charge pump output current. 23 VREF Internal Compensation Node. VREF is dc biased at half of the tuning range. Connect decoupling capacitors to the ground plane as close to this pin as possible. The recommended capacitor values are 10 pF, 1 nF, and 4.7 µF. 24 VBIAS Reference Voltage. Connect decoupling capacitors to the ground plane as close to this pin as possible. The recommended capacitor values are 10 pF, 1 nF, and 1 µF. 25, 32 CREG1, CREG2 Outputs from the LDO Regulator. Pin 25 and Pin 32 are the supply voltages to the digital circuits, and have a nominal voltage of 1.8 V. Decoupling capacitors of 100 nF connected to AGND are required for these pins. 26 PDBRF RF Power-Down. A logic low on this pin mutes the RF outputs. This mute function is also software-controllable. 27 DVDD Digital Power Supply. This pin must be at the same voltage as AVDD. Place decoupling capacitors to the ground plane as close to this pin as possible. For optimum spurious performance, VRF and DVDD must originate from different regulators. 28 REFINB Complementary Reference Input. If unused, ac-couple this pin to AGND. 29 REFINA Reference Input. 30 MUXOUT Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or the scaled reference frequency to be externally accessible. 31 SDGND Digital Σ-Δ Modulator Ground. Pin 31 is the ground return path for the Σ-Δ modulator. EP Exposed Pad. The exposed pad must be connected to AGND. |
类似零件编号 - ADF4355-3BCPZ |
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类似说明 - ADF4355-3BCPZ |
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