AD5675RBCPZ-REEL7 datasheet(8/32 Pages) AD

部件名	AD5675RBCPZ-REEL7

功能描述	Base station power amplifiers

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制造商	AD [Analog Devices]

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AD5671R/AD5675R

Data Sheet

Rev. B | Page 8 of 32

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, all specifications −40°C to +125°C, unless otherwise noted.

Table 5.

Parameter1, 2

Min

Max

Unit

Description

t1

0.92

µs

SCL cycle time

t2

0.11

µs

tHIGH, SCL high time

t3

0.44

µs

tLOW, SCL low time

t4

0.04

µs

tHD,STA, start/repeated start hold time

t5

40

ns

tSU,DAT, data setup time

t63

−0.04

µs

tHD,DAT, data hold time

t7

−0.045

µs

tSU,STA, repeated start setup time

t8

0.195

µs

tSU,STO, stop condition setup time

t9

0.12

µs

tBUF, bus free time between a stop condition and a start condition

t104

0

ns

tR, rise time of SCL and SDA when receiving

t114, 5

20 + 0.1CB

ns

tF, fall time of SCL and SDA when transmitting/receiving

t12

20

ns

LDAC pulse width

t13

0.4

ns

SCL rising edge to LDAC rising edge

t14

4.8

ns

RESET minimum pulse width low, 1.8 V ≤ VLOGIC ≤ 2.7 V

6.2

ns

RESET minimum pulse width low, 2.7 V ≤ VLOGIC ≤ 5.5 V

t15

132

ns

RESET activation time, 1.8 V ≤ VLOGIC ≤ 2.7 V

80

ns

RESET activation time, 2.7 V ≤ VLOGIC ≤ 5.5 V

tSP6

0

ns

Pulse width of suppressed spike

CB5

400

pF

Capacitive load for each bus line

1

See Figure 2.

2

Guaranteed by design and characterization; not production tested.

3

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the minimum VIH of the SCL signal) to bridge the undefined region of the

SCL falling edge.

4

tR and tF are measured from 0.3 × VDD to 0.7 × VDD.

5

CB is the total capacitance of one bus line in pF.

6

Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.

Timing Diagrams

Figure 2. 2-Wire Serial Interface Timing Diagram

Figure 3. RESET Timing Diagram

SCL

SDA

t1

t3

LDAC1

LDAC2

START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

NOTES

1ASYNCHRONOUS LDAC UPDATE MODE.

2SYNCHRONOUS LDAC UPDATE MODE.

t4

t6

t5

t7

t8

t2

t13

t4

t11

t10

t12

t9

RESET

t14

t15

VOUTx

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