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AD83C151C-12 数据表(PDF) 11 Page - TEMIC Semiconductors |
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AD83C151C-12 数据表(HTML) 11 Page - TEMIC Semiconductors |
11 / 24 page 80C154/83C154 Rev.F (14 Jan. 97) 11 MATRA MHS 32 Bit Counter Figure 13 illustrates the 32 bit COUNTER mode. Figure 12. 32 Bit Counter Configuration. D In this mode, T32 = 0 and C/T0 = 1. Before it can make an increment, the 83C154 µ must detect two transitions on its T0 input. As shown in figure 14, input T0 is sampled on each S5P2 state of every machine cycle or, in other words, every OSC ÷ 12. Figure 13. Counter Incrementation Condition. D The counter will only evolve if a level 1 is detected during state S5P2 of cycle Ci and if a level 0 is detected during state S5P2 of cycle Ci + n. D Consequently, the minimal period of signal fEXT admissible by the counter must be greater than or equal to two machine cycles. The following formula should be used to calculate the operating frequency. f + fEXT 65536 (T0,T1) fEXT t OSC 24 Watchdog Mode D WDT = 1 enables access to this mode. As shown in figure 15, all the modes of TIMERS 0 and 1, of which the overflows act on TF1 (TF1 = 1), activate the WATCHDOG Mode. Figure 14. The Different Watchdog Configurations. |
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