Rev 0.7 9/14

Copyright © 2014 by Silicon Laboratories

Si50122-A3/A4

Si50122-A3/A4

Features

Applications

Description

Si50122-A3/A4 is a high performance, crystal-less PCIe clock generator

that can generate two 100 MHz PCIe clock and one 25 MHz LVCMOS

clock outputs. The differential clock outputs are compliant to PCIe Gen1

and Gen 2 specifications. The ultra-small footprint (2.0x2.5 mm) and

industry leading low power consumption make Si50122-A3/A4 the ideal

clock solution for consumer and embedded applications where board

space is limited and low power is needed.

Functional Block Diagram

integrated CMEMS

HCSL outputs

LVCMOS output

100 MHz

buffers

for differential output clocks

profile for maximum EMI

reduction (Si50122-A4)

85 °C

(2.0x2.5 mm)

spread spectrum outputs

spread outputs

Divider

VDD

CMEMS

REFOUT

PLL 

(SSC)

DIFF1

DIFF2

VSS

Patents pending

Ordering Information:

See page 10

Pin Assignments

10

9

8

7

1

2

3

4

VSS

REFOUT

NC

5

6

VSS

DIFF2

DIFF2

DIFF1

DIFF1

VDD

VDD