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Si534fA 数据表(PDF) 7 Page - Silicon Laboratories |
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Si534fA 数据表(HTML) 7 Page - Silicon Laboratories |
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7 / 62 page  Si5345/44/42 Rev. 1.0 7 REFCLK Frequency fIN_REF Frequency range for best output jitter performance 48 — 54 MHz TCXO frequency for SyncE applications. Jitter perfor- mance may be reduced —40 — MHz Input Single-ended Volt- age Swing VIN_SE 365 — 2000 mVpp_se Input Differential Voltage Swing VIN_DIFF 365 2500 mVpp_diff Slew rate2, 3 SR 400 — — V/µs Input Duty Cycle DC 40 — 60 % Table 3. Input Specifications (Continued) (VDD =1.8 V ±5%, VDDA =3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Voltage swing is specified as single-ended mVpp. 2. Imposed for jitter performance. 3. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 – 0.2) x VIN_Vpp_se) / SR 4. This mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz that must be dc-coupled because they have a duty cycle significantly less than 50%. A typical application example is a low-frequency video frame sync pulse. Since the input thresholds (VIL, VIH) of this buffer are non-standard (0.33 and 0.49 V, respectively) refer to the input attenuator circuit for dc-coupled pulsed LVCMOS in the Family Reference Manual at: www.silabs.com/ Support%20Documents/TechnicalDocs/Si5345-44-42-RM.pdf. Otherwise, for standard LVCMOS input clocks, use the Standard Differential or Single-Ended ac-coupled input mode. OUTx OUTx Vpp_se Vpp_se Vpp_diff = 2*Vpp_se Vcm Vcm |
类似零件编号 - Si534fA |
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类似说明 - Si534fA |
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