Si3050-EVB

Rev. 1.1

3

2. Configuring the Si-LINK

The Si-LINK motherboard is used to interface the

Si3050 to a PC or other audio system for easy

evaluation. It uses an FPGA to translate the parallel port

interface to either SPI/PCM, SPI-only, or GCI to

communicate with the Si3050.

When in SPI/PCM mode, the PCM audio data and SPI

control data are communicated from the controlling PC

using the aforementioned software. This mode allows

the user to evaluate the DAA without any lab equipment

other than a PC.

By selecting SPI-only operation, the PC is still used to

control the DAA through the SPI bus, but the PCM

audio data is routed from an external source. This

external source may be an Audio Precision system

using the P1 and P2 headers or a PCM highway using

the BNC connectors, J5–J8 (not populated).

To evaluate the Si3050’s operation with the GCI

interface, the PC may be used to send the audio data

and control. The FPGA performs the necessary

translation to communicate to the Si3050 in this mode.

The fourth mode of operation is the pass-thru mode. In

this mode, the FPGA is only used to route the GCI bus

to the Audio Precision or BNC headers on the Si-LINK

board. In this mode, a PC is not required to control the

evaluation platform.

3. Configuring the Si3050DC-EVB

The Si3050DC-EVB has six jumpers. The first five

control the boot-strap options for configuring the

Si3050. The default state is set to allow the Si3050 to be

controlled using the SPI bus. See Figure 1.

Figure 1. SPI Control Mode Default State

By changing the jumper configuration prior to powering

the board, the mode of the board can be set according

to Tables 1–3.

JP10 is the sixth jumper on the Si-LINK motherboard.

Moving this jumper to the INT position routes pin 9 of

the Si3050 to the Si-LINK motherboard. When the

jumper is in the AOUT position, this signal is routed to

the optional call progress speaker system, which is not

populated by default on the evaluation platform. Refer to

the AOUT PWM circuit in the Si3050 data sheet for

values used to populate this circuit.

Mode

JP3 (Source)

JP4 (Format)

SPI/PCM

0

0

SPI-Only

1

0

GCI

0

1

Pass-Thru

1

1

0 SCLK 1

0 SDI_THRU 1

0CS

1

0

SDO 1

0

SDI

1

Table 1. PCM or GCI Highway Mode Selection

SCLK

SDI

Mode Selected

1

X

PCM Mode

0

0

GCI Mode,

B2 Channel used

0

1

GCI Mode,

B1 Channel used

Note: Values shown are the states of the pins at the

rising edge of RESET.

Table 2. Pin Functionality in PCM or GCI

Highway Mode

Pin Name

PCM Mode

GCI Mode

SDI_THRU SPI Data Through-

put pin for Daisy

Chaining Operation

(Connects to the SDI

pin of the subse-

quent device in the

daisy chain)

Sub-frame

Selector, bit 2

SCLK

SPI Clock Input

PCM/GCI Mode

Selector

SDI

SPI Serial Data Input B1/B2 Channel

Selector

SDO

SPI Serial Data Out-

put

Sub-frame

Selector, bit 1

CS

SPI Chip Select

Sub-frame

Selector, bit 0

FSYNC

PCM Frame Sync

Input

GCI Frame Sync

Input

PCLK

PCM Input Clock

GCI Input Clock

DTX

PCM Data Transmit

GCI Data Transmit

DRX

PCM Data Receive

GCI Data Receive

Note: This table denotes pin functionality after the rising

edge of RESET and mode selection.