EEPROM

1.8V LVCMOS

CLK input

GND

Input Clock

Vctr

S0

Programming

and

SDA/SCL Register

Y2 = 3-state

Y1 = 3-state

Y3 = 3-state

LV

CMOS

Pdiv1 = 1

LV

CMOS

Pdiv3 = 0

(disabled)

Pdiv2 = 0

(disabled)

PLL Bypass

LV

CMOS

PLL 1 enabled

SDA

SCL

LVCMOS

Programming Bus

^1_ = outputs 3-State

^0_ = outputs 3-State

11

CDCE813-Q1

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SNAS705 – JANUARY 2017

Product Folder Links: CDCE813-Q1

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Copyright © 2017, Texas Instruments Incorporated

(1)

State0 and State1 are user definable in the generic configuration

register and can be power down, Hi-Z state, low, or active.

Y1

FUNCTION

0

State 0

1

State 1

The S1/SDA and S2/SCL pins of the CDCE813-Q1 device are dual-function pins. In the default configuration,

they are defined as SDA and SCL for the serial programming interface. They can be programmed as control pins

(S1 and S2) by setting the appropriate bits in the EEPROM.

NOTE

Changes to the control register (Bit [6] of byte 02h) have no effect until they are written

into the EEPROM.

forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA and SCL).

S0 is not a multi-use pin; it is a control pin only.

9.3.2 Default Device Configuration

The internal EEPROM of the CDCE813-Q1 device is pre-configured with a factory default configuration as shown

in Figure 5 (the input frequency is routed through PLL1 to the outputs as a default). This mode can be used to

clean the jitter of an incoming clock signal. However the outputs are disabled by default and need to be turned

on through I2C or with S0 pin.

The default setting appears either after power is supplied or after a power-down – power-up sequence until it is

reprogrammed by the user to a different application configuration. A new register setting is programmed through

the serial I2C interface.

Figure 5. Default Configuration

Table 6 shows the factory default setting for the Control Terminal Register.

NOTE

Even though eight different register settings are possible, in the default configuration, only

the first two settings (0 and 1) can be selected with S0, as S1 and S2 are configured as

programming pins in default mode.