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MC14093BDR2G 数据表(PDF) 1 Page - ON Semiconductor

部件名 MC14093BDR2G
功能描述  Quad 2-Input
Download  8 Pages
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制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor

MC14093BDR2G 数据表(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 10
1
Publication Order Number:
MC14093B/D
MC14093B
Quad 2-Input “NAND"
Schmitt Trigger
The MC14093B Schmitt trigger is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14093B
may be used in place of the MC14011B quad 2−input NAND gate for
enhanced noise immunity or to “square up” slowly changing
waveforms.
Features
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load Over the Rated Temperature
Range
Triple Diode Protection on All Inputs
Pin−for−Pin Compatible with CD4093
Can be Used to Replace MC14011B
Independent Schmitt−Trigger at each Input
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
− 0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
− 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 1)
500
mW
TA
Ambient Temperature Range
− 55 to +125
°C
Tstg
Storage Temperature Range
− 65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
MARKING DIAGRAMS
SOIC−14
TSSOP−14
1
14
14093BG
AWLYWW
14
093B
ALYW
G
G
1
14
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
G or
G
= Pb−Free Package
SOEIAJ−14
1
14
MC14093B
ALYWG
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
SOIC−14
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
SOEIAJ−14
F SUFFIX
CASE 965
PIN ASSIGNMENT
11
12
13
14
8
9
10
5
4
3
2
1
7
6
OUTC
OUTD
IN 1D
IN 2D
VDD
IN 1C
IN 2C
OUTB
OUTA
IN 2A
IN 1A
VSS
IN 2B
IN 1B


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