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DAC38RF90 数据表(PDF) 55 Page - Texas Instruments |
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DAC38RF90 数据表(HTML) 55 Page - Texas Instruments |
55 / 152 page 16 16 16 16 xN xN xN xN x sin(x) 48-bit NCO2 cos sin 48-bit NCO1 cos sin CMIX control (±n*Fs/4) Input Mux Multiband summation x sin(x) PAP Gain PAP Gain From 2nd multi-DUC Delay I Q I Q Path AB Path CD 55 DAC38RF80, DAC38RF83, DAC38RF84 DAC38RF85, DAC38RF90, DAC38RF93 www.ti.com SLASEA3 – DECEMBER 2016 Product Folder Links: DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Figure 49. DAC38RFxx multi-DUC Signal Processing Block Diagram 8.3.17.1 Multi-DUC input Each multi-DUC, accepts data from up to 8 Serdes lanes. A crossbar switch allows any Serdes lane to be mapped to any other Serdes lane. The crossbar switch is controlled by fields OCTETPATHx_SEL (x = [0..7]) in Registers JESD_CROSSBAR1 (8.5.57) and JESD_CROSSBAR2 (8.5.58). As shown in Table 9, the multiband DUC can be configured as either a single DUC with 1 IQ input, or a dual DUC with 2 IQ inputs, which is selected by asserting field DUAL_IQ in register MULTIDUC_CFG1 (8.5.13). 8.3.17.2 Interpolation Filters The digital upconverter first increases the sample rate of the IQ signal from the input sample rate to the final DAC sample rate through a series of interpolation filters. Different sets of filters are used to achieve different rates, as shown in Table 34. The interpolation rate is selected by field INTERP in register MULTIDUC_CFG1 (8.5.13). Table 34. FIR filters Used for Different Interpolation Rates FILTERS USED Interpolation Rate FIR0 (2x) FIR1 (2x) LPFIR0_5X FIR2 (2x) LPFIR0_3X FIR3 (2x) LPFIR1_3X 6 x x 8 x x x x 10 x x 12 x x x 16 x x x x 18 x x x 20 x x x 24 x x x x |
类似零件编号 - DAC38RF90 |
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类似说明 - DAC38RF90 |
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