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MC14099B 数据表(PDF) 1 Page - ON Semiconductor

部件名 MC14099B
功能描述  8-Bit Addressable Latches
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制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor

MC14099B 数据表(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 9
1
Publication Order Number:
MC14099B/D
MC14099B
8-Bit Addressable Latches
The MC14099B is an 8−bit addressable latch. Data is entered in
serial form when the appropriate latch is addressed (via address pins
A0, A1, A2) and write disable is in the low state. For the MC14099B
the input is a unidirectional write only port.
The data is presented in parallel at the output of the eight latches
independently of the state of Write Disable, Write/Read or Chip
Enable.
A Master Reset capability is available on both parts.
Features
Serial Data Input
Parallel Output
Master Reset
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−power TTL Loads or One
Low−Power Schottky TTL Load over the Rated Temperature
Range
MC14099B pin for pin compatible with CD4099B
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
− 0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
− 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
− 55 to +125
°C
Tstg
Storage Temperature Range
− 65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
MARKING DIAGRAM
SOIC−16 WD
DW SUFFIX
CASE 751G
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Indicator
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
14099BG
AWLYYWW
16
1
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
Q3
Q4
Q5
Q6
VDD
Q0
Q1
Q2
WRITE
DISABLE
DATA
RESE
T
Q7
VSS
A2
A1
A0
PIN ASSIGNMENT


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