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MC74HC161ADT 数据表(PDF) 11 Page - ON Semiconductor |
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MC74HC161ADT 数据表(HTML) 11 Page - ON Semiconductor |
11 / 16 page P0 P1 P2 P3 ENABLE P ENABLE T RESET T0 R C C LOAD LOAD P0 Q0 Q0 Q1 Q2 Q3 RIPPLE CARRY OUT VCC= PIN 16 GND = PIN 8 14 The flip–flops shown in the circuit diagrams are Toggle–Enable flip–flops. A Toggle– Enable flip–flop is a combination of a D flip–flop and a T flip–flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip–flop. The logic level at the Pn input is then clocked to the Q output of the flip–flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip–flop low. Q0 Q1 Q1 Q2 Q2 Q3 T1 R C C LOAD LOAD P1 T2 R C C LOAD LOAD P2 T3 R C C LOAD LOAD P3 13 12 11 15 3 4 5 6 7 10 1 9 2 R C C LOAD LOAD CLOCK LOAD |
类似零件编号 - MC74HC161ADT |
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类似说明 - MC74HC161ADT |
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