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TSB82AA2I 数据表(PDF) 10 Page - Texas Instruments |
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TSB82AA2I 数据表(HTML) 10 Page - Texas Instruments |
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10 / 104 page  1−2 efficient than its predecessors, thus providing an overall reduction in the device’s operational power requirements especially when operating in D3cold using auxiliary power. In fact, the TSB82AA2 device fully supports D0, D1, D2, and D3hot/cold power states as specified in the PC 2001 Design Guide requirements and the PCI Power Management Specification. PME wake event support is subject to operating system support and implementation. As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a−2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles as specified by the PCI Local Bus Specification, and provides plug-and-play (PnP) compatibility. Furthermore, the TSB82AA2 device is fully compliant with the latest PCI Local Bus Specification, PCI Bus Power Management Interface Specification, IEEE Draft Std 1394b, IEEE Std 1394a−2000, and 1394 Open Host Controller Interface Specification (see Section 1.3, Related Documents, for a complete list). 1.2 Features The TSB82AA2 device supports the following features: • Single 3.3-V supply (1.8-V internal core voltage with regulator) • 3.3-V and 5-V PCI signaling environments • Serial bus data rates of 100M bits/s, 200M bits/s, 400M bits/s, and 800M bits/s • Physical write posting of up to three outstanding transactions • Serial ROM or boot ROM interface supports 2-wire serial EEPROM devices • 33-MHz/64-bit and 33-MHz/32-bit selectable PCI interface • Multifunction terminal (MFUNC terminal 1): − PCI_CLKRUN protocol per the PCI Mobile Design Guide − General-purpose I/O − CYCLEIN/CYCLEOUT for external cycle timer control for customized synchronization • PCI burst transfers and deep FIFOs to tolerate large host latency: − Transmit FIFO—5K asynchronous − Transmit FIFO—2K isochronous − Receive FIFO—2K asynchronous − Receive FIFO—2K isochronous • D0, D1, D2, and D3 power states and PME events per the PCI Bus Power Management Interface Specification • Programmable asynchronous transmit threshold • Isochronous receive dual-buffer mode • Out-of-order pipelining for asynchronous transmit requests • Register access fail interrupt when the PHY SYSCLK is not active • Initial bandwidth available and initial channels available registers • Digital video and audio performance enhancements • Fabricated in advanced low-power CMOS process • Packaged in 144-terminal LQFP (PGE) |
类似零件编号 - TSB82AA2I |
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类似说明 - TSB82AA2I |
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