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M74HC166B1R 数据表(PDF) 1 Page - STMicroelectronics |
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M74HC166B1R 数据表(HTML) 1 Page - STMicroelectronics |
1 / 13 page M54HC166 M74HC166 October 1992 8 BIT PISO SHIFT REGISTER B1R (Plastic Package) ORDER CODES : M54HC166F1R M74HC166M1R M74HC166B1R M74HC166C1R F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN CONNECTIONS (top view) NC = No Inter- nal Con- DESCRIPTION . HIGH SPEED fMAX = 57 MHz (TYP.) AT VCC =5 V . LOW POWER DISSIPATION ICC =4 µA (MAX.) AT TA =25 °C . HIGH NOISE IMMUNITY VNIH =VNIL =28 % VCC (MIN.) . OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS . SYMMETRICAL OUTPUT IMPEDANCE |IOH|= IOL = 4 mA (MIN.) . BALANCED PROPAGATION DELAYS tPLH =tPHL . WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V . PIN AND FUNCTION COMPATIBLE WITH 54/74LS166 The M54/74HC166 is a high speed C 2MOS 8 BIT PISO SHIFT REGISTER fabricated in silicon gate C 2MOS technology. It has the same high speed per- formance of LSTTL combined with true CMOS low power consumption. It consists of parallel or serial inputs and a serial-out 8-bit shift register with gated clock inputs and an overriding clear input. The parallel-in or serial-in modes are controlled by the SHIFT/LOAD input. When the SHIFT/LOAD input is held high, the serial data input is enabled and the eight flip-flops perform serial shifting with each clock pulse. When held low, the parallel data inputs are enabled and syn- chronous loading occurs on the next clock pulse. Clocking is accomplished on the low-to-high level edge of the clock pulse. The CLOCK-INHIBIT input should be changed to the high only while the CLOCK input is held high. A direct clear input over- rides all other inputs, including the clock, and sets all flip-flops to zero. Functional details are shown in the truth table and the timing chart. All inputs are equipped with protection circuits against static discharge and transient excess volt- age. 1/13 |
类似零件编号 - M74HC166B1R |
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类似说明 - M74HC166B1R |
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