数据搜索系统,热门电子元器件搜索 |
|
LM2453TA 数据表(PDF) 8 Page - National Semiconductor (TI) |
|
|
LM2453TA 数据表(HTML) 8 Page - National Semiconductor (TI) |
8 / 14 page Application Hints (Continued) Effect of Load Capacitance Figure 10 shows the effect of increased load capacitance on the speed of the device. This demonstrates the importance of knowing the load capacitance in the application. It is im- portant to note that the rise time of the series R in the test cir- cuit in Figure 4 along with the load capacitance will increase its contribution to the speed degradation as the load capaci- tance is increased. The previous section discussed how to optimize the transient response in the application with the use of a series inductor. Effect of Offset Figure 9 shows the variation in rise and fall times when the output offset of the device is varied from 40 VDC to 50 VDC. The rise time shows a maximum variation relative to the cen- ter data point (45 VDC) of less than 4%. The fall time shows a variation of less than 10% relative to the center data point. It is recommended that the video black level be set about 10V below the V CC power supply in the application (Black level at ∼70 with V CC =80 VDC). This will give the best over- all performance while also minimizing the DC power dissipa- tion. DC CLAMP AMPLIFIERS The portion of the multiplexed input signal that is below the reference voltage controls the DC clamp amplifiers. The DC transfer function of the amplifier is shown in Figure 12. Fig- ure 15 shows the application circuit for the clamp amplifier. Clamp diode D1 is placed as close as possible to the video node to minimize trace lengths and parasitic capacitance. Pull-up resistor R1 is required to bias the PNP output stage of the clamp circuit. Capacitor C2 provides a low impedance at high frequencies and helps minimize clamp level variation that could be caused by changes in the cathode current. INTEGRATED BOOST SUPPLY AND G1 BLANK CIRCUIT Upon initial power up the G1 V blank/Cap Low input will sink current until the boost capacitor is charged up to approxi- mately 74V (V CC1–VG1-L). After this initial charge up period, the voltage across the boost capacitor will be replenished during the vertical blank interval. The charge cycle will be initiated by the V blank input signal (negative going, logic level pulse). Figure 16 shows the boost application circuit. During the charge cycle the voltage at pin 4 will be set to ∼6V and capacitor C28 will be charged to ∼74V through diode D11. When the charge cycle is com- pleted, the voltage at pin 4 will be set to ∼49V and the plus side of the boost cap will be at ∼123 V DC. Capacitor C29 will then be charged to ∼122.3V (0.7V below 123) through D12. Diode D12 is required to avoid turning on the ESD protection diodes between the video clamp outputs and the 120V pin during the charge cycle. C29 is required to maintain the 120V at pin 2 during the charge cycle. The 43 Vp-p pulse at pin 4 can be ac-coupled to G1 of the CRT to blank the CRT during vertical retrace. The recom- mended application circuit for doing this is shown in Figure 18. THERMAL CONSIDERATIONS Figure 6 shows the performance of the LM2453 video ampli- fiers in the test circuit shown in Figure 4 as a function of case temperature. The figure shows that the rise time of the LM2453 decreases by approximately 6% as the case tem- perature increases from 50˚C to 100˚C. This corresponds to a speed degradation of 1.2% for every 10˚C rise in case tem- perature. There is a negligible change in fall time versus temperature in the test circuit. Figure 8 shows the total power dissipation of the LM2453 vs. frequency when all three video channels of the device are driving an 8 pF or 12 pF load with a 40 V p-p signal. The graph assumes a 72% active time (device operating at the speci- fied frequency) which is typical in a monitor application. The other 28% of the time the device is assumed to be sitting at the black level (65V in this case). This graph gives the de- signer the information needed to determine the heat sink re- quirement for his application. It is important to note that the capacitive load dramatically effects the AC component of the total power dissipation. The LM2453 case temperature must be maintained below 100˚C. If the maximum expected ambient temperature is 50˚C and the maximum power dissipation is 8.5W, then a maximum heat sink thermal resistance can be calculated: This example assumes a capacitive load of 8 pF, no resistive load and a maximum operating frequency of 50 MHz or greater. THE NSC REFERENCE DESIGN Figures 17, 18, 19 show the schematic and layout for the NSC Neck Board Reference Design. It contains a complete video channel from monitor input to CRT cathode. Perfor- mance is ideal for 1280 X 1024 resolution displays with pixel clock frequencies up to 135 MHz. A sample of this design along with all necessary support hardware and materials can be obtained from your local sales office. DS101302-21 FIGURE 15. Clamp Application Circuit. DS101302-20 FIGURE 16. Boost Circuit Schematic www.national.com 8 |
类似零件编号 - LM2453TA |
|
类似说明 - LM2453TA |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |