MC100LVELT22

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2

1

2

3

45

6

7

8

D0

GND

Q0

D1

Q1

Q1

Q0

LVPECL

LVTTL/

LVCMOS

Figure 1. 8−Lead Pinout (Top View) and Logic Diagram

PIN

FUNCTION

Table 1. PIN DESCRIPTION

Qn, Qn

LVPECL Differential Outputs

D0, D1

LVTTL/LVCMOS Inputs

Positive Supply

GND

Ground

Table 2. ATTRIBUTES

Characteristics

Value

Internal Input Pulldown Resistor

N/A

Internal Input Pullup Resistor

N/A

ESD Protection

Human Body Model

Machine Model

> 4 kV

> 200 V

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

SOIC−8

TSSOP−8

Level 1

Level 3

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V−0 @ 0.125 in

Transistor Count

164

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 3. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

Positive Power Supply

GND = 0 V

7

V

Input Voltage

GND = 0 V

7

V

Output Current

Continuous

Surge

50

100

mA

mA

Operating Temperature Range

−40 to +85

°C

Storage Temperature Range

−65 to +150

°C

Thermal Resistance (Junction−to−Ambient)

0 lfpm

500 lfpm

SO−8

SO−8

190

130

°C/W

°C/W

Thermal Resistance (Junction−to−Case)

std bd

SO−8

41 to 44

± 5%

°C/W

Thermal Resistance (Junction−to−Ambient)

0 lfpm

500 lfpm

TSSOP−8

TSSOP−8

185

140

°C/W

°C/W

Thermal Resistance (Junction−to−Case)

std bd

TSSOP−8

41 to 44

± 5%

°C/W

Wave Solder

Pb−Free

<2 to 3 sec @ 260

°C

265

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)