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ADPD103BCPZRL 数据表(PDF) 8 Page - Analog Devices |
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ADPD103BCPZRL 数据表(HTML) 8 Page - Analog Devices |
8 / 53 page Data Sheet ADPD103 Rev. B | Page 7 of 52 Parameter Test Conditions/Comments Min Typ Max Unit SYSTEM PERFORMANCE Total Output Noise Floor Normal mode; per pulse; per channel; no LED; CPD = 70 pF 25 kΩ; referred to ADC input 2.0 LSB rms 25 kΩ; referred to peak input signal for 2 µs LED pulse 4.6 nA rms 25 kΩ; referred to peak input signal for 3 µs LED pulse 3.3 nA rms 25 kΩ; saturation signal-to-noise ratio (SNR) per pulse per channel4 72.3 dB 50 kΩ; referred to ADC input 2.4 LSB rms 50 kΩ; referred to peak input signal for 2 µs LED pulse 2.8 nA rms 50 kΩ; referred to peak input signal for 3 µs LED pulse 2.0 nA rms 50 kΩ; saturation SNR per pulse per channel4 70.6 dB 100 kΩ; referred to ADC input 3.4 LSB rms 100 kΩ; referred to peak input signal for 2 µs LED pulse 1.9 nA rms 100 kΩ; referred to peak input signal for 3 µs LED pulse 1.4 nA rms 100 kΩ; saturation SNR per pulse per channel4 67.6 dB 200 kΩ; referred to ADC input 5.5 LSB rms 200 kΩ; referred to peak input signal for 2 µs LED pulse 1.6 nA rms 200 kΩ; referred to peak input signal for 3 µs LED pulse 1.1 nA rms 200 kΩ; saturation SNR per pulse per channel4 63.5 dB DC Power Supply Rejection Ratio (DC PSRR) −37 dB 1 This saturation level applies to the ADC only and, therefore, includes only the pulsed signal. Any nonpulsatile signal is removed prior to the ADC stage. 2 ADC resolution is listed per pulse when the AFE offset is correctly compensated per the AFE Operation section. If using multiple pulses, divide by the number of pulses. 3 This saturation level applies to the full signal path and, therefore, includes both the ambient signal and the pulsed signal. 4 The noise term of the saturation SNR value refers to the receive noise only and does not include photon shot noise or any noise on the LED signal itself. DIGITAL SPECIFICATIONS DVDD = 1.7 V to 1.9 V, unless otherwise noted. Table 5. Parameter Symbol Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS (SCL, SDA) Input Voltage Level High VIH 0.7 × DVDD 3.6 V Low VIL 0.3 × DVDD V Input Current Level High IIH −10 +10 µA Low IIL −10 +10 µA Input Capacitance CIN 10 pF LOGIC OUTPUTS INT Output Voltage Level High VOH 2 mA high level output current DVDD − 0.5 V Low VOL 2 mA low level output current 0.5 V PDSO Output Voltage Level High VOH 2 mA high level output current DVDD − 0.5 V Low VOL 2 mA low level output current 0.5 V SDA Output Voltage Level Low VOL1 2 mA low level output current 0.2 × DVDD V SDA Output Current Level Low IOL VOL1 = 0.6 V 6 mA |
类似零件编号 - ADPD103BCPZRL |
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类似说明 - ADPD103BCPZRL |
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