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ADPD103BCPZ 数据表(PDF) 6 Page - Analog Devices |
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ADPD103BCPZ 数据表(HTML) 6 Page - Analog Devices |
6 / 53 page Data Sheet ADPD103 Rev. B | Page 5 of 52 PERFORMANCE SPECIFICATIONS AVDD = DVDD = 1.8 V, TA = full operating temperature range, unless otherwise noted. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit DATA AQUISITION Resolution Single pulse 14 Bits Resolution/Sample 64 to 255 pulses 20 Bits Resolution/Data Read 64 to 255 pulses and sample average = 128 27 Bits LED DRIVER LED Current Slew Rate1 Rise Slew rate control setting = 0; TA = 25°C; ILED = 70 mA 240 mA/µs Slew rate control setting = 7; TA = 25°C; ILED = 70 mA 1400 mA/µs Fall Slew rate control setting = 0, 1, 2; TA = 25°C; ILED = 70 mA 3200 mA/µs Slew rate control setting = 6, 7; TA = 25°C; ILED = 70 mA 4500 mA/µs LED Peak Current LED pulse enabled 8 250 mA Driver Compliance Voltage Voltage above ground required for LED driver operation 0.2 V LED PERIOD AFE width = 4 µs 19 µs AFE width = 3 µs 17 µs Sampling Frequency2 Time Slot A only; normal mode; 1 pulse; OFFSET_LEDA = 23 µs; PERIOD_LEDA = 19 µs 0.122 3230 Hz Time Slot B only; normal mode; 1 pulse; OFFSET_LEDA = 23 µs; PERIOD_LEDA = 19 µs 0.122 3820 Hz Both time slots; normal mode; 1 pulse; OFFSET_LEDA = 23 µs; PERIOD_LEDA = 19 µs 0.122 1750 Hz Time Slot A only; normal mode; 8 pulses; OFFSET_LEDA = 23 µs; PERIOD_LEDA = 19 µs 0.122 2257 Hz Time Slot B only; normal mode; 8 pulses; OFFSET_LEDA = 23 µs; PERIOD_LEDA = 19 µs 0.122 2531 Hz Both time slots; normal mode; 8 pulses; OFFSET_LEDA = 23 µs; PERIOD_LEDA = 19 µs 0.122 1193 Hz CATHODE PIN (PDC) VOLTAGE During All Sampling Periods Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 13 1.8 V Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0 1.3 V During Slot A Sampling Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x03 1.8 V Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x1 1.3 V Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x2 1.55 V Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x34 0 V During Slot B Sampling Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x03 1.8 V Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x1 1.3 V Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x2 1.55 V Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x34 0 V During Sleep Periods Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 1 1.8 V Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0 1.3 V Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x0 1.8 V Register 0x54, Bit 7 = 0x1; Register 0x54[13:12] = 0x1 1.3 V Register 0x54, Bit 7 = 0x1; Register 0x54[13:12] = 0x2 1.55 V Register 0x54, Bit 7 = 0x1; Register 0x54[13:12] = 0x3 0 V PHOTODIODE INPUT PINS/ ANODE VOLTAGE During All Sampling Periods 1.3 V During Sleep Periods Cathode voltage V 1 LED inductance is negligible for these values. The effective slew rate slows with increased inductance. 2 The maximum values in this specification are the internal ADC sampling rates in normal mode. The I2C read rates in some configurations may limit the actual output data rate of the device 3 This mode may induce additional noise and is not recommended unless absolutely necessary. The 1.8 V setting uses VDD, which contains greater amounts of differential voltage noise with respect to the anode voltage. A differential voltage between the anode and cathode injects a differential current across the capacitance of the photodiode of the magnitude C × dV/dt. 4 This setting is not recommended for photodiodes because it causes a 1.3 V forward bias of the photodiode. |
类似零件编号 - ADPD103BCPZ |
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类似说明 - ADPD103BCPZ |
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