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ADP7157ACPZ-04-R7 数据表(PDF) 1 Page - Analog Devices |
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ADP7157ACPZ-04-R7 数据表(HTML) 1 Page - Analog Devices |
1 / 24 page 1.2 A, Ultralow Noise, High PSRR, RF Linear Regulator Data Sheet ADP7157 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Input voltage range: 2.3 V to 5.5 V Adjustable output voltage range (V OUT): 1.2 V to 3.3 V Maximum load current: 1.2 A Low noise 0.9 µV rms typical output noise from 100 Hz to 100 kHz 1.6 µV rms typical output noise from 10 Hz to 100 kHz Noise spectral density: 1.7 nV/√Hz from 10 kHz to 1 MHz Power supply rejection ratio (PSRR) 82 dB from 1 kHz to 100 kHz 55 dB at 1 MHz Dropout voltage: 120 mV typical at I OUT = 1.2 A, VOUT = 3.3 V Initial accuracy: ±0.6% at I LOAD = 10 mA Accuracy over line, load, and temperature: ±1.5% Operating supply current (I GND) 4.0 mA typical at 0 µA 7.0 mA typical at 1.2 A Low shutdown current: 0.2 μA typical Stable with a 10 µF ceramic output capacitor 10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages Precision enable Supported by ADIsimPower tool APPLICATIONS Regulation to noise sensitive applications: phase-locked loops (PLLs), voltage controlled oscillators (VCOs), and PLLs with integrated VCOs Communications and infrastructure Backhaul and microwave links GENERAL DESCRIPTION The ADP7157 is an adjustable linear regulator that operates from 2.3 V to 5.5 V and provides up to 1.2 A of output current. Output voltages from 1.2 V to 3.3 V are possible depending on the model. Using an advanced proprietary architecture, the device provides high power supply rejection and ultralow noise, achieving excellent line and load transient response with only a 10 µF ceramic output capacitor. The ADP7157 is available in four models that optimize power dissipation and PSRR performance as a function of the input and output voltage. See Table 9 and Table 10 for selection guides. The typical output noise the ADP7157 regulator is 0.9 μV rms from 100 Hz to 100 kHz and 1.7 nV/√Hz for noise spectral density from 10 kHz to 1 MHz. The ADP7157 is available in 10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages, making it not only a very compact solution, but also providing excellent thermal performance for applications requiring up to 1.2 A of output current in a small, low profile footprint. TYPICAL APPLICATION CIRCUIT EN BYP VREG ADP7157 REF_SENSE VIN VOUT VOUT_SENSE COUT 10µF VOUT = 3.3V REF GND CIN 10µF CREG 1µF CBYP 1µF CREF 1µF R1 VOUT = 1.2V × (R1 + R2)/R2 1kΩ < R2 < 200kΩ R2 VIN = 3.8V ON OFF Figure 1. Regulated 3.3 V Output from a 3.8 V Input Table 1. Related Devices Model Input Voltage Output Current Fixed/ Adjustable Package ADP7159 , ADP7158 2.3 V to 5.5 V 2 A Fixed 10-lead LFCSP/ 8-lead SOIC ADP7156 2.3 V to 5.5 V 1.2 A Fixed/ Adjustable 10-lead LFCSP/ 8-lead SOIC ADM7150, ADM7151 4.5 V to 16 V 800 mA Fixed/ Adjustable 8-lead LFCSP/ 8-lead SOIC ADM7154, ADM7155 2.3 V to 5.5 V 600 mA Fixed/ Adjustable 8-lead LFCSP/ 8-lead SOIC ADM7160 2.2 V to 5.5 V 200 mA Fixed 6-lead LFCSP/ 5-lead TSOT 0.1 1 10 100 1k 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) CBYP = 1µF CBYP = 10µF CBYP = 100µF CBYP = 1000µF Figure 2. Noise Spectral Density at Different Values of CBYP, VOUT = 3.3 V |
类似零件编号 - ADP7157ACPZ-04-R7 |
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类似说明 - ADP7157ACPZ-04-R7 |
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