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DSC400-0241Q0001KE2T Datasheet(数据表) 8 Page - Microchip Technology

部件型号  DSC400-0241Q0001KE2T
说明  Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
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DSC400-0241Q0001KE2T Datasheet(HTML) 8 Page - Microchip Technology

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 8 page
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DSC400
DS20005612A-page 8
 2016 Microchip Technology Inc.
4.3
HCSL
FIGURE 4-3:
Typical HCSL Termination Scheme.
RS is a series resistor implemented to match the trace impedance. Depending on the board layout, the value may range
from 0Ω to 30Ω.
Note 1:
See the Output Waveform section for more information.
2:
The addition of IDDCORE and IDDIO provides the total current consumption of the device.
TABLE 4-3:
HCSL OUTPUTS
Parameter
Symbol
Min.
Typ.
Max.
Units
Condition
Output Logic
Levels
VOH
0.725
V
Output Logic High, RL = 50Ω
VOL
0.1
Output Logic Low, RL = 50Ω
Peak-to-Peak
Output Swing
750
mV
Single-Ended
Output
Transition Time
(Note 1)
tR
200
400
ps
Rise Time, 20% to 80%, RL= 50Ω,
CL= 2 pF
tF
200
400
Fall Time, 20% to 80%, RL= 50Ω,
CL= 2 pF
Frequency
f0
2.3
460
MHz
Single Frequency
Output Duty
Cycle
SYM
48
52
%
Differential
IO Supply
Current (Note 2)
IDDIO
20
22
mA
Per Output at 125 MHz.
Period Jitter
JPER
—2.5
psRMS
Integrated
Phase Noise
JPH
—0.25—
psRMS 200 kHz to 20 MHz @ 156.25 MHz
0.37
100 kHz to 20 MHz @ 156.25 MHz
1.7
2.0
12 kHz to 20 MHz @156.25 MHz
100 Ω
50 Ω
50 Ω
RS
RS




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