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AD8305ACP Datasheet(数据表) 9 Page  Analog Devices 

9 page REV. A AD8305 –9– GENERAL STRUCTURE The AD8305 addresses a wide variety of interfacing conditions to meet the needs of fiber optic supervisory systems, and will also be useful in many nonoptical applications. These notes explain the structure of this unique style of translinear log amp. Figure 1 is a simplified schematic showing the key elements. TEMPERATURE COMPENSATION (SUBTRACT AND DIVIDE BY T K BIAS GENERATOR VLOG COMM VNEG (NORMALLY GROUNDED) VSUM INPT 0.5V 80k 0.5V 0.5V VBE2 VBE2 VBE1 VBE1 44 A/dec IREF IPD 6.69k Q2 Q1 PHOTODIODE INPUT CURRENT COMM 20k 451 VREF VRDZ IREF 14.2k 2.5V Figure 1. Simplified Schematic The photodiode current IPD is received at Pin INPT. The voltage at this node is essentially equal to those on the two adjacent guard pins, VSUM and IREF, due to the low offset voltage of the JFET op amp. Transistor Q1 converts the input current IPD to a corresponding logarithmic voltage, as shown in Equation 1. A finite positive value of VSUM is needed to bias the collector of Q1 for the usual case of a singlesupply voltage. This is internally set to 0.5 V, that is, one fifth of the reference voltage of 2.5 V appearing on Pin VREF. The resistance at the VSUM pin is nominally 16 k W; this voltage is not intended as a general bias source. The AD8305 also supports the use of an optional negative supply voltage, VN, at Pin VNEG. When VN is –0.5 V or more negative, VSUM may be connected to ground; thus INPT and IREF assume this potential. This allows operation as a voltageinput logarithmic converter by the inclusion of a series resistor at either or both inputs. Note that the resistor setting IREF will need to be adjusted to maintain the intercept value. It should also be noted that the collectoremitter voltages of Q1 and Q2 are now the full VN, and effects due to selfheating will cause errors at large input currents. The input dependent VBE1 of Q1 is compared with the reference VBE2 of a second transistor, Q2, operating at IREF. This is gener ated externally, to a recommended value of 10 mA. However, other values over a severaldecade range can be used with a slight degradation in law conformance (TPC 1). Theory The baseemitter voltage of a BJT (bipolar junction transistor) can be expressed by Equation 1, which immediately shows its basic logarithmic nature: VkT q I I BE C S = () // In (1) where IC is its collector current, IS is a scaling current, typically only 10 –17 A, and kT/q is the thermal voltage, proportional to absolute temperature (PTAT) and is 25.85 mV at 300 K. The current, IS, is never precisely defined and exhibits an even stron ger temperature dependence, varying by a factor of roughly a billion between –35 ∞C and +85∞C. Thus, to make use of the BJT as an accurate logarithmic element, both of these tempera ture dependencies must be eliminated. The difference between the baseemitter voltages of a matched pair of BJTs, one operating at the photodiode current IPD and the second operating at a reference current IREF, can be written as: VV kT q I I kT q I I kT q I I mV I I T K CS REF S PD REF PD REF BE1 BE2 –/ / – / / / log / . log / = () ( ) = () ( ) = () = () In In In 10 59 5 300 10 10 (2) The uncertain and temperature dependent saturation current IS, which appears in Equation 1, has thus been eliminated. To eliminate the temperature variation of kT/q, this difference voltage is processed by what is essentially an analog divider. Effectively, it puts a variable under Equation 2. The output of this process, which also involves a conversion from voltagemode to current mode, is an intermediate, temperaturecorrected current: II I I LOG Y PD REF = () log / 10 (3) where IY is an accurate, temperaturestable scaling current that determines the slope of the function (the change in current per decade). For the AD8305, IY is 44 mA, resulting in a temperature independent slope of 44 mA/decade, for all values of IPD and IREF. This current is subsequently converted back to a voltagemode output, VLOG, scaled 200 mV/decade. It is apparent that this output should be zero for IPD = IREF, and would need to swing negative for smaller values of input current. To avoid this, IREF would need to be as small as the smallest value of IPD. However, it is impractical to use such a small refer ence current as 1 nA. Accordingly, an offset voltage is added to VLOG to shift it upward by 0.8 V when Pin VRDZ is directly connected to VREF. This has the effect of moving the intercept to the left by four decades, from 10 mA to 1 nA: II I I LOG Y PD INTC = () log / 10 (4) where IINTC is the operational value of the intercept current. To disable this offset, Pin VRDZ should be grounded, then the intercept IINTC is simply IREF. Since values of IPD < IINTC result in a negative VLOG, a negative supply of sufficient value is required to accommodate this situation (discussed later). The voltage VLOG is generated by applying ILOG to an internal resistance of 4.55 k W, formed by the parallel combination of a 6.69 k W resistor to ground and the 14.2 kW resistor to the VRDZ pin. When the VLOG pin is unloaded and the intercept reposi tioning is disabled by grounding VRDZ, the output current ILOG generates a voltage at the VLOG pin of: VI AI VI LOG LOG REF Y REF =¥ =¥ ¥ () = () 455 44 4 55 10 10 .k .k log / log / W W m I I PD PD (5) where VY = 200 mV/decade, or 10 mV/dB. Note that any resistive loading on VLOG will lower this slope and also result in an overall scaling uncertainty due to the variability of the onchip resistors. Consequently, this practice is not recommended. VLOG may also swing below ground when dual supplies (VP and VN) are used. When VN = –0.5 V or larger, the input pins INPT and IREF may now be positioned at ground level by simply grounding VSUM. 
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