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DAC7573IPWR 数据表(PDF) 11 Page - Texas Instruments |
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DAC7573IPWR 数据表(HTML) 11 Page - Texas Instruments |
11 / 30 page www.ti.com _ + Resistor String Ref+ Ref− DAC Register VOUT 50 kW 50 kW VREFH VREFL 70 kW V OUT + VREFL ) (VREFH * VREFL) D 4096 (1) VREFH To Output Amplifier R R R R VREFL DAC7573 SLAS398 – SEPTEMBER 2003 THEORY OF OPERATION D/A SECTION The architecture of the DAC7573 consists of a string DAC followed by an output buffer amplifier. Figure 29 shows a generalized block diagram of the DAC architecture. Figure 29. R-String DAC Architecture The input coding to the DAC7573 is unsigned binary, which gives the ideal output voltage as: Where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 4095. RESISTOR STRING The resistor string section is shown in Figure 30. It is basically a divide-by-2 resistor, followed by a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. Because the architecture consists of a string of resistors, it is specified monotonic. Figure 30. Typical Resistor String Output Amplifier The output buffer is a gain-of-2 noninverting amplifier, capable of generating rail-to-rail voltages on its output, which gives an output range of 0V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/µs with a half-scale settling time of 8 µs with the output unloaded. I2C Interface I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. 11 |
类似零件编号 - DAC7573IPWR |
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类似说明 - DAC7573IPWR |
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