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TPL5010 数据表(PDF) 5 Page - Texas Instruments |
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TPL5010 数据表(HTML) 5 Page - Texas Instruments |
5 / 22 page 5 TPL5010-Q1 www.ti.com SNAS679 – SEPTEMBER 2016 Product Folder Links: TPL5010-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) Values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. (2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method. (3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. (4) The supply current excludes load and pull-up resistor current. Input pins are at GND or VDD. (5) This parameter is specified by design and/or characterization and is not tested in production. (6) The accuracy for time interval settings below 1 second is ±100 ms. (7) Operational life time test procedure equivalent to 10 years. 7.5 Electrical Characteristics TA= 25°C, VDD-GND=2.5 V (unless otherwise stated) (1) PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT POWER SUPPLY IDD Supply current(4) Operation mode 35 50 nA Digital conversion of external resistance (Rext) 200 400 µA TIMER tIP Time interval period(5) 1650 selectable time Intervals Min time interval 100 ms Max time interval 7200 s Time interval setting accuracy(6) Excluding the precision of Rext ±0.6% Timer interval setting accuracy over supply voltage 1.8 V ≤ VDD ≤ 5.5 V ±25 ppm/V tOSC Oscillator accuracy –0.5% 0.5% Oscillator accuracy over temperature(5) -40°C ≤ TA ≤ 125°C 150 ppm/°C Oscillator accuracy over supply voltage(5) 1.8 V ≤ VDD ≤ 5.5 V ±0.4 %/V Oscillator accuracy over life time(7) 0.24% tDONE Minimum DONE pulse width (5) 100 ns tRSTn RSTn pulse width 320 ms tWAKE WAKE pulse width 20 ms t_Rext Time to convert Rext(5) 100 ms DIGITAL LOGIC LEVELS VIH Minimum logic high threshold DONE pin 0.7 × VDD V VIL Maximum logic low threshold DONE pin 0.3 × VDD V VOH Logic output high-level WAKE pin Iout = 100 µA VDD – 0.3 V Iout = 1 mA VDD – 0.7 V VOL Logic output low-level WAKE pin Iout = –100 µA 0.3 V Iout = –1 mA 0.7 V VOLRSTn RSTn logic output low-level IOL= –1 mA 0.3 V IOHRSTn RSTn high-level output current VOHRSTn = VDD 1 nA VIHM_RST Minimum logic high threshold DELAY/M_RST pin(5) 1.5 V |
类似零件编号 - TPL5010 |
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类似说明 - TPL5010 |
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