数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

AD1555-AD1556 数据表(PDF) 11 Page - Analog Devices

部件名 AD1555-AD1556
功能描述  24-Bit ADC WITH LOW NOISE PGA
Download  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD1555-AD1556 数据表(HTML) 11 Page - Analog Devices

Back Button AD1555-AD1556 Datasheet HTML 7Page - Analog Devices AD1555-AD1556 Datasheet HTML 8Page - Analog Devices AD1555-AD1556 Datasheet HTML 9Page - Analog Devices AD1555-AD1556 Datasheet HTML 10Page - Analog Devices AD1555-AD1556 Datasheet HTML 11Page - Analog Devices AD1555-AD1556 Datasheet HTML 12Page - Analog Devices AD1555-AD1556 Datasheet HTML 13Page - Analog Devices AD1555-AD1556 Datasheet HTML 14Page - Analog Devices AD1555-AD1556 Datasheet HTML 15Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 24 page
background image
REV. B
AD1555/AD1556
–11–
AD1556 PIN FUNCTION DESCRIPTIONS (continued)
Pin No.
Mnemonic
Description
14
DOUT
Serial Data Output. DOUT is used to access the conversion results or the contents of the Status
Register, depending on the logic state of the RSEL pin. At the beginning of a read operation, the
first data bit is output (MSB first). The data changes on the rising edge of SCLK and is valid on the
SCLK falling edge.
15
DRDY
Data Ready. A logic high output indicates that data is ready to be accessed from the Output Data
Register. DRDY goes low once a read operation is complete. When selected, the DRDY output pin
has a type buffer that allows wired-OR connection of multiple AD1556s.
16
CS
Chip Select. When set low the serial data interface pins DIN, DOUT, R/
W, and SCLK are active; a
logic high disables these pins and sets the DOUT pin to Hi-Z.
17
R/
W
Read/Write. A read operation is initiated if R/
W is high and CS is low. A low sets the DOUT pin to
Hi-Z and allows a write operation to the device via the DIN pin.
18
RSEL
Register Select. When set high, the Conversion Data Register contents are output on a read opera-
tion. A low selects the Status Register.
19
DIN
Serial Data Input. Used during a write operation. Loads the Configuration Register via the Input
Shift Register. Data is loaded MSB first and must be valid on the falling edge of SCLK.
20
ERROR
Error Flag. A logic low output indicates an error condition occurred in the modulator or digital
filter. When
ERROR goes low the ERROR bit in the status register is set high. The ERROR output
pin has an open drain type buffer with an internal 100 k
Ω typical pull-up that allows wired-OR
connection of multiple AD1556s.
25
RESET
Chip Reset. A logic high input clears any error condition in the status register and sets the configuration
register to the state of the corresponding hardware pins. On power-up, this reset state is entered.
26
PWRDN
Power-Down Hardware Control. A logic high input powers down the filter. The convolution cycles
in the digital filter and the MCLK signal are stopped. All registers retain their data and the serial
data interface remains active. The power-down mode is entered on the first falling edge of CLKIN
after PWRDN is taken high. When exiting the power-down mode, a SYNC must be applied to
resume filter convolutions.
29
CSEL
Filter Input Select. Selects the source for input to the digital filter. A logic high selects the TDATA
input, a low selects MDATA as the filter input.
30
TDATA
Test Data. Input to digital filter for user test data.
31
SYNC
Synchronization Input. The SYNC input clears the AD1556 filter in order to synchronize the start
of the filter convolutions. The SYNC event is initiated on the first CLKIN rising edge after the
SYNC pin goes high. The SYNC input can also be applied synchronously to the AD1556 decima-
tion rate without resetting the convolution cycles.
32
CLKIN
Clock Input. The clock input signal, nominally 1.024 MHz, provides the necessary clock for the
AD1556. This clock frequency is divided by four to generate the MCLK signal for the AD1555.
35
MCLK
Modulator Clock. Provides the modulator sampling clock frequency. The modulator always samples
at one-fourth the CLKIN frequency.
36
MDATA
Modulator Data. This input receives the ones-density bit stream from the AD1555 for input to the
digital filter.
37
RESETD
Decimator Reset. A logic high resets the decimator of the digital filter.
38
MFLG
Modulator Error. The MFLG input is used to detect if an overrange condition occurred in the
modulator. Its logic level is sensed on the rising edge of CLKIN. When overrange condition
detected, ERROR goes low and updates the status register.
43–39
CB0–CB4
Modulator Control. These output control pins represent a portion of the data loaded into the AD1556
Configuration Register. CB0–CB2 are generally used to set the PGA gain or cause it to enter in the
PGA standby mode (Refer to Table III). CB3 and CB4 select the mux input voltage applied to the
PGA as described in Table III.


类似零件编号 - AD1555-AD1556

制造商部件名数据表功能描述
logo
Analog Devices
AD1555/56-REF AD-AD1555/56-REF Datasheet
435Kb / 24P
   24-Bit - ADC with Low Noise PGA
REV. B
AD1555AP AD-AD1555AP Datasheet
435Kb / 24P
   24-Bit - ADC with Low Noise PGA
REV. B
AD1555APRL AD-AD1555APRL Datasheet
435Kb / 24P
   24-Bit - ADC with Low Noise PGA
REV. B
AD1555APZRL AD-AD1555APZRL Datasheet
435Kb / 24P
   24-Bit - ADC with Low Noise PGA
REV. B
AD1555BP AD-AD1555BP Datasheet
435Kb / 24P
   24-Bit - ADC with Low Noise PGA
REV. B
More results

类似说明 - AD1555-AD1556

制造商部件名数据表功能描述
logo
Analog Devices
AD1556 AD-AD1556_15 Datasheet
435Kb / 24P
   24-Bit ADC with Low Noise PGA
REV. B
AD1555APZRL AD-AD1555APZRL Datasheet
435Kb / 24P
   24-Bit - ADC with Low Noise PGA
REV. B
AD1555 AD-AD1555_15 Datasheet
435Kb / 24P
   24-Bit ADC with Low Noise PGA
REV. B
AD7190 AD-AD7190 Datasheet
178Kb / 21P
   4.8 kHz Ultra-Low Noise 24-Bit Sigma-Delta ADC with PGA
Rev.PrD 7/08
AD7193 AD-AD7193_17 Datasheet
1Mb / 57P
   24-Bit Sigma-Delta ADC with PGA
AD7194 AD-AD7194_17 Datasheet
1Mb / 55P
   24-Bit Sigma-Delta ADC with PGA
AD7190 AD-AD7190_08 Datasheet
749Kb / 40P
   4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA
REV. 0
AD7192 AD-AD7192 Datasheet
711Kb / 40P
   4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
REV. A
AD7124-4 AD-AD7124-4 Datasheet
1Mb / 90P
   4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
AD7124-8 AD-AD7124-8 Datasheet
1Mb / 91P
   8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com