数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

GS4576C09 数据表(PDF) 10 Page - GSI Technology

部件名 GS4576C09
功能描述  64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM (LLDRAM II)
Download  62 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  GSI [GSI Technology]
网页  http://www.gsitechnology.com
标志 GSI - GSI Technology

GS4576C09 数据表(HTML) 10 Page - GSI Technology

Back Button GS4576C09 Datasheet HTML 6Page - GSI Technology GS4576C09 Datasheet HTML 7Page - GSI Technology GS4576C09 Datasheet HTML 8Page - GSI Technology GS4576C09 Datasheet HTML 9Page - GSI Technology GS4576C09 Datasheet HTML 10Page - GSI Technology GS4576C09 Datasheet HTML 11Page - GSI Technology GS4576C09 Datasheet HTML 12Page - GSI Technology GS4576C09 Datasheet HTML 13Page - GSI Technology GS4576C09 Datasheet HTML 14Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 62 page
background image
GS4576C09/18/36L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 11/2013
10/62
© 2011, GSI Technology
DLL Reset
Mode Register Bit 7 (M7) selects DLL Reset as is shown in the Mode Register Definition tables. The default setting for M7 is Low,
whereby the DLL is disabled. Once M7 is set High, 1024 cycles (5
s at 200 MHz) are needed before a Read command can be
issued. The delay allows the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur
may result in a violation of the tCKQK parameter. A reset of the DLL is necessary if tCK or VDD is changed after the DLL has
already been enabled. To reset the DLL, set M7 is Low. After waiting tMRSC, an MRS command should be issued to set M7 High.
1024 clock cycles must pass before loading the next Read command.
Driver Impedance Mapping
The LLDRAM II is equipped with programmable impedance output buffers. Setting Mode Register Bit 8 (M8) High during the
MRS command activates the feature. Programmable impedance output buffers allow the user to match the driver impedance to the
PCB trace impedance. To adjust the impedance, an external resistor (RQ) is connected between the ZQ ball and V
SS. The value of
the resistor must be five times the desired impedance (e.g., a 300
 resistor produces an output impedance of 60). RQ values of
125
–300 are supported, allowing an output impedance range of 25–60 (+/- 15 %).
The drive impedance of uncompensated output transistors can change over time due to changes in supply voltage and die
temperature. When drive impedance control is enabled in the MRS, the value of RQ is periodically sampled and any needed
impedance update is made automatically. Updates do not affect normal device operation or signal timing.
When Bit M8 is set Low during the MRS command, the output compensation circuits are still active but reference an internal
resistance reference. The internal reference is imprecise and subject to temperature and voltage variations so output buffers are set
to a nominal output impedance of 50
, but are subject to a ±30 percent variance over the Commercial temperature range of the
device.


类似零件编号 - GS4576C09

制造商部件名数据表功能描述
logo
GSI Technology
GS4576C09GL-18 GSI-GS4576C09GL-18 Datasheet
2Mb / 63P
   576Mb CIO Low Latency DRAM (LLDRAM II)
GS4576C09GL-24 GSI-GS4576C09GL-24 Datasheet
2Mb / 63P
   576Mb CIO Low Latency DRAM (LLDRAM II)
GS4576C09GL-25 GSI-GS4576C09GL-25 Datasheet
2Mb / 63P
   576Mb CIO Low Latency DRAM (LLDRAM II)
GS4576C09GL-33 GSI-GS4576C09GL-33 Datasheet
2Mb / 63P
   576Mb CIO Low Latency DRAM (LLDRAM II)
GS4576C09L-18 GSI-GS4576C09L-18 Datasheet
2Mb / 63P
   576Mb CIO Low Latency DRAM (LLDRAM II)
More results

类似说明 - GS4576C09

制造商部件名数据表功能描述
logo
GSI Technology
GS4288C09 GSI-GS4288C09 Datasheet
2Mb / 62P
   32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II
GS4576C36GL-25I GSI-GS4576C36GL-25I Datasheet
2Mb / 63P
   576Mb CIO Low Latency DRAM (LLDRAM II)
logo
Integrated Silicon Solu...
IS42S86400B ISSI-IS42S86400B Datasheet
913Kb / 61P
   64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM
logo
Mosel Vitelic, Corp
V54C3256164VALT6 MOSEL-V54C3256164VALT6 Datasheet
838Kb / 52P
   256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
V54C3256 MOSEL-V54C3256 Datasheet
853Kb / 52P
   256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
logo
Integrated Silicon Solu...
IS61DDB42M18 ISSI-IS61DDB42M18 Datasheet
515Kb / 26P
   36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB22M18 ISSI-IS61DDB22M18 Datasheet
550Kb / 25P
   36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
logo
Elpida Memory
MC-4R64FKE8D-840 ELPIDA-MC-4R64FKE8D-840 Datasheet
458Kb / 14P
   Direct Rambus DRAM RIMM Module 64M-BYTE (32M-WORD x 18-BIT)
MC-4R64FKE8D ELPIDA-MC-4R64FKE8D Datasheet
135Kb / 14P
   Direct Rambus DRAM RIMM Module 64M-BYTE (32M-WORD x 18-BIT)
logo
Integrated Silicon Solu...
IS61DDB22M36 ISSI-IS61DDB22M36 Datasheet
624Kb / 25P
   72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com