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MAX5590 数据表(PDF) 28 Page - Maxim Integrated Products |
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MAX5590 数据表(HTML) 28 Page - Maxim Integrated Products |
28 / 33 page Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs 28 ______________________________________________________________________________________ SET, MID, CLR The SET, MID, and CLR signals force the DAC outputs to full scale, midscale, or zero scale (Figure 5). These signals cannot be active at the same time. The active-low SET input forces the DAC outputs to full scale when SET is low. When SET is high, the DAC out- puts follow the data in the DAC registers. The active-low MID input forces the DAC outputs to midscale when MID is low. When MID is high, the DAC outputs follow the data in the DAC registers. The active-low CLR input forces the DAC outputs to zero scale when CLR is low. When CLR is high, the DAC outputs follow the data in the DAC registers. If CLR, MID, or SET signals go low during a write com- mand, reload the data to ensure accurate results. Power-Down Lockout ( PDL) The PDL active-low, software-shutdown lockout input overrides (not overwrites) the PD_0 and PD_1 shutdown- mode bits. PDL cannot be active at the same time as SHDN1K or SHDN100K (see the Shutdown Mode (SHDN1K, SHDN100K) section). If the PD_0 and PD_1 bits command the DAC to shut down prior to PDL going low, the DAC returns to shutdown mode immediately after PDL goes high, unless the PD_0 and PD_1 bits were modified through the serial interface in the meantime. Shutdown Mode ( S SH HD DN N1 1K K, S SH HD DN N1 10 00 0K K) The SHDN1K and SHDN100K are active-low signals that override (not overwrite) the PD_1 and PD_0 bit set- tings. For the MAX5590/MAX5592/MAX5594, drive SHDN1K low to select shutdown mode with OUTA– OUTH internally terminated with 1k Ω to ground, or drive SHDN100K low to select shutdown with an internal 100k Ω termination. For the MAX5591/MAX5593/ MAX5595, drive SHDN1K low for shutdown with 1k Ω output termination, or drive SHDN100K low for shut- down with high-impedance outputs. For proper shutdown, first select a shutdown mode (Table 8), then use the shutdown-control bits as listed in Table 2b. Data Output (DOUTRB, DOUTDC0, DOUTDC1) UPIO1 and UPIO2 can be configured as serial data out- puts, DOUTRB (data out for read back), DOUTDC0 (data out for daisy-chaining, mode 0), and DOUTDC1 (data out for daisy-chaining, mode 1). The differences between DOUTRB and DOUTDC0 (or DOUTDC1) are as follows: • The source of read-back data on DOUTRB is the DOUT register. Daisy-chain DOUTDC_ data comes directly from the shift register. • Read-back data on DOUTRB is only present after a DAC read command. Daisy-chain data is present on DOUTDC_ for any DAC write after the first 16 bits are written. • The DOUTRB idle state (CS = high) for read back is high impedance. Daisy-chain DOUTDC_ idles high when inactive to avoid floating the data input in the next device in the daisy-chain. See Figures 1 and 2 for timing details. tGP tLDS END OF CYCLE* GPO_ LDAC * END-OF-CYCLE REPRESENTS THE RISING EDGE OF CS OR THE 16TH ACTIVE CLOCK EDGE, DEPENDING ON THE MODE OF OPERATION. tCMS tLDL tS ±0.5 LSB TOGG VOUT_ LDAC PDL CLR, MID, OR SET PDL AFFECTS DAC OUPTUTS (VOUT_) ONLY IF DACS WERE PREVIOUSLY SHUT DOWN. Figure 5. Asynchronous Signal Timing Figure 6. GPO_ and LDAC Signal Timing |
类似零件编号 - MAX5590 |
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类似说明 - MAX5590 |
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