GS81314PD18/36GK-133/120/106

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.09 5/2016

4/39

© 2014, GSI Technology

Pin Description

Symbol

Description

Type

SA[21:1]

Address — Read or write address is registered on

CK.

Input

D[35:0]

Write Data — Registered on

KD and KD during Write operations.

D[17:0] - x18 and x36.

D[35:18] - x36 only.

Input

DINV[3:0]

Write Data Inversion — Registered on

KD and KD (along with write data) during Write operations. 

Indicate if the associated write data byte is inverted (DINVx = 1) or not (DINVx = 0).

DINV0 - associated with D[8:0] in x18 and x36.

DINV1 - associated with D[17:9] in x18 and x36.

DINV2 - associated with D[26:18] in x36 only.

DINV3 - associated with D[35:27] in x36 only.

Note: Treated as NU inputs when Data Inversion is disabled.

Input

Q[35:0]

Read Data — Aligned with

CQ and CQ during Read operations.

Q[17:0] - x18 and x36.

Q[35:18] - x36 only.

Output

QINV[3:0]

Read Data Inversion — Aligned with

CQ and CQ (along with read data) during Read operations. 

Indicate if the associated read data byte is inverted (QINVx = 1) or not (QINVx = 0).

QINV0 - associated with Q[8:0] in x18 and x36.

QINV1 - associated with Q[17:9] in x18 and x36.

QINV2 - associated with Q[26:18] in x36 only.

QINV3 - associated with Q[35:27] in x36 only.

Note: Treated as NU outputs when Data Inversion is disabled.

Output

QVLD[1:0]

Read Data Valid — Driven high one half cycle before valid read data.

Output

CK, CK

Primary Input Clocks — Dual single-ended. Used for latching address and control inputs, for internal timing

control, and for output timing control.

Input

KD[1:0],

KD[1:0]

Write Data Input Clocks — Dual single-ended. Used for latching write data inputs.

KD0, KD0: latch D[17:0], DINV[1:0] in x36, and D[8:0], DINV0 in x18.

KD1, KD1: latch D[35:18], DINV[3:2] in x36, and D[17:9], DINV1 in x18.

Input

CQ[1:0],

CQ[1:0]

Read Data Output Clocks — Free-running output (echo) clocks, tightly aligned with read data outputs.

Facilitate source-synchronous operation.

CQ0, CQ0: align with Q[17:0], QINV[1:0] in x36, and Q[8:0], QINV0 in x18.

CQ1, CQ1: align with Q[35:18], QINV[3:2] in x36, and Q[17:9], QINV1 in x18.

Output

R

Read Enable — Registered on

CK. See the Clock Truth Table for functionality.

Input

W

Write Enable — Registered on

CK. See the Clock Truth Table for functionality.

Input

MRW

Mode Register Write — Registered on

CK. Can be used synchronously or asynchronously to enable Reg-

ister Write Mode. See the State and Clock Truth Tables for functionality.

Input

PLL

PLL Enable — Weakly pulled High internally.

PLL = 0: disables internal PLL.

PLL = 1: enables internal PLL.

Input

RST

Reset — Holds the device inactive and resets the device to its initial power-on state when asserted High.

Weakly pulled Low internally.

Input