CY7C1354B
CY7C1356B
Document #: 38-05114 Rev. *C
Page 20 of 29
Capacitance[16]
Parameter
Description
Test Conditions
BGA Max.
fBGA Max.
TQFP Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VDD = 3.3V VDDQ = 2.5V
555
pF
CCLK
Clock Input Capacitance
5
5
5
pF
CI/O
Input/Output Capacitance
7
7
5
pF
AC Test Loads and Waveforms
Thermal Resistance[16]
Parameters
Description
Test Conditions
BGA Typ.
fBGA Typ.
TQFP Typ.
Unit
Notes
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per EIA
/ JESD51.
25
27
25
°C/W
17
ΘJC
Thermal Resistance
(Junction to Case)
669
°C/W
17
Switching Characteristics Over the Operating Range [21, 22]
Parameter
Description
-225
-200
-166
Unit
Min.
Max.
Min.
Max.
Min.
Max.
tPower[17]
VCC (typical) to the First Access Read or
Write
1
11
ms
Clock
tCYC
Clock Cycle Time
4.4
56
ns
FMAX
Maximum Operating Frequency
225
200
166
MHz
tCH
Clock HIGH
1.8
2.0
2.4
ns
tCL
Clock LOW
1.8
2.0
2.4
ns
Output Times
tCO
Data Output Valid after CLK Rise
2.8
3.2
3.5
ns
tEOV
OE LOW to Output Valid
2.8
3.2
3.5
ns
tDOH
Data Output Hold after CLK Rise
1.25
1.5
1.5
ns
tCHZ
Clock to High-Z[18, 19, 20]
1.25
2.81.5
3.21.5
3.5
ns
tCLZ
Clock to Low-Z[18, 19, 20]
1.25
1.5
1.5
ns
tEOHZ
OE HIGH to Output High-Z[18, 19, 20]
2.8
3.2
3.5
ns
tEOLZ
OE LOW to Output Low-Z[18, 19, 20]
0
00
ns
Shaded areas contain advance information.
Notes:
16. Tested initially and after any design or process changes that may affect these parameters.
17. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be
initiated.
18. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
19. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
20. This parameter is sampled and not 100% tested.
21. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
DQ
R=1667/317
Ω
R = 1538/351
Ω
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
RL = 50Ω
Z0 = 50Ω
VL = 1.5V/1.25V
VDDQ
ALL INPUT PULSES
[16]
0V
90%
10%
90%
10%
< 1.0 ns
< 1.0 ns
(c)
VDD
1.5/1.25V
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
