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CY7C1354B 数据表(PDF) 2 Page - Cypress Semiconductor

部件名 CY7C1354B
功能描述  9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
Download  29 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY7C1354B 数据表(HTML) 2 Page - Cypress Semiconductor

  CY7C1354B Datasheet HTML 1Page - Cypress Semiconductor CY7C1354B Datasheet HTML 2Page - Cypress Semiconductor CY7C1354B Datasheet HTML 3Page - Cypress Semiconductor CY7C1354B Datasheet HTML 4Page - Cypress Semiconductor CY7C1354B Datasheet HTML 5Page - Cypress Semiconductor CY7C1354B Datasheet HTML 6Page - Cypress Semiconductor CY7C1354B Datasheet HTML 7Page - Cypress Semiconductor CY7C1354B Datasheet HTML 8Page - Cypress Semiconductor CY7C1354B Datasheet HTML 9Page - Cypress Semiconductor Next Button
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CY7C1354B
CY7C1356B
Document #: 38-05114 Rev. *C
Page 2 of 29
Selection Guide
CY7C1354B-225
CY7C1356B-225
CY7C1354B-200
CY7C1356B-200
CY7C1354B-166
CY7C1356B-166
Unit
Maximum Access Time
2.8
3.2
3.5
ns
Maximum Operating Current
250
220
180
mA
Maximum CMOS Standby Current
35
35
35
mA
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
A0, A1, A
C
MODE
BWa
BWb
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQPa
DQPb
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CEN
WRITE
DRIVERS
ZZ
Sleep
Control
Logic Block Diagram-CY7C1356B (512K x 18)


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