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Si8284CD-IS 数据表(PDF) 4 Page - Silicon Laboratories

部件名 Si8284CD-IS
功能描述  4.0 Amp ISODrivers with Integrated DC-DC Converters
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制造商  SILABS [Silicon Laboratories]
网页  http://www.silabs.com
标志 SILABS - Silicon Laboratories

Si8284CD-IS 数据表(HTML) 4 Page - Silicon Laboratories

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2.3 Input
The IN+ and IN– inputs to the Si828x devices act as a complementary pair. If the IN– is held low, the IN+ will act as a active-high input
for the driver control. Alternatively, if IN+ is held high, then the IN– can be used as an active-low input for driver control. When the IN– is
used as the control signal, taking the IN+ low will hold the output driver low.
IN+
VH
_
IN
VL
HIGH
LOW
HIGH
LOW
Pull-up
Hi-Z
Hi-Z
Pull-down
Figure 2.2. Si828x Complementary Input Diagram
2.4 Driver Side Output
The Si828x has separate pins for gate drive high (VH) and gate drive low (VL). This makes it simple for the user to use different gate
resistors to control IGBT VCE rise and fall time.
2.5 Fault (FLTb) Pin
FLTb is an open-drain type output. Once the UVLO condition is cleared on the driver side of the device, the FLTb pin is released. A
pull-up resistor takes the pin high. When the desaturation condition is detected, the Si828x indicates the fault by bringing the FLTb pin
low. FLTb stays low until the controller brings the RSTb pin low.
FLTb is also taken low if the UVLO condition is met during device operation. FLTb is released in that case as soon as the UVLO condi-
tion is cleared.
2.6 Reset (RSTb) Pin
The RSTb pin is used to clear the desaturation condition and bring the Si828x driver back to an operational state. Even though the input
may be toggling, the driver will not change state until the fault condition has been reset.
2.7 Ready (RDY) Pin
The ready pin indicates to the controller that power is available on both sides of the isolation, i.e., at VDDA and VDDB. RDY goes high
when both the primary side and secondary side UVLO circuits are disengaged. If the UVLO conditions are met on either side of the
isolation barrier, the ready pin will return low. RDY is a push-pull output pin and can be floated if not used.
2.8 Undervoltage Lockout (UVLO)
The UVLO circuit unconditionally drives VL low when VDDB is below the lockout threshold. The Si828x is maintained in UVLO until
VDDB rises above VDDBUV+. During power down, the Si828x enters UVLO when VDDB falls below the UVLO threshold plus hysteresis
(i.e., VDDB < VDDBUV+ – VDDBHYS).
Si8281/82/83/84 Data Sheet
System Overview
silabs.com | Smart. Connected. Energy-friendly.
Preliminary Rev. 0.5 | 3


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