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Si5345-D-EVB 数据表(PDF) 6 Page - Silicon Laboratories |
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Si5345-D-EVB 数据表(HTML) 6 Page - Silicon Laboratories |
6 / 60 page 3.4.1 Initialization and Reset Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa- tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits including the serial interface will be restored to their initial state. A hard reset is initiated using the RSTb pin or by asserting the hard reset register bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. No valid input clocks selected Lock Acquisition (Fast Lock) Locked Mode Holdover Mode Phase lock on selected input clock is achieved An input is qualified and available for selection No valid input clocks available for selection Free-run Valid input clock selected Reset and Initialization Power-Up Selected input clock fails Yes No Holdover History Valid? Other Valid Clock Inputs Available? No Yes Input Clock Switch Figure 3.1. Modes of Operation 3.4.2 Freerun Mode The DSPLL will automatically enter freerun mode once power is applied to the device and initialization is complete. The frequency ac- curacy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the external crystal or refer- ence clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in freerun mode. Any drift of the crystal frequency will be tracked at the output clock frequencies. A TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in freerun or holdover modes. 3.4.3 Lock Acquisition Mode The device monitors all inputs for a valid clock. If at least one valid clock is available for synchronization, the DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, the DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls in to the input clock frequency. 3.4.4 Locked Mode Once locked, the DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point, any XTAL frequency drift will not affect the output frequency. A loss of lock pin (LOL) and status bit indicate when lock is ach- ieved. See 3.8.4 LOL Detection for more details on the operation of the loss-of-lock circuit. Si5345/44/42 Rev D Data Sheet Functional Description silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 5 |
类似零件编号 - Si5345-D-EVB |
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类似说明 - Si5345-D-EVB |
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