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GS2986 数据表(PDF) 8 Page - Semtech Corporation |
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GS2986 数据表(HTML) 8 Page - Semtech Corporation |
8 / 41 page GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 8 of 41 1.3 Default Start-up Settings The GS2986 has some functions that are not accessible via direct pin control, and are only accessible through the host interface registers. These functions have an internal pull-up or pull-down resistor that sets the default logic level or start-up state, if it is not already set by a pin. If the user wishes to override these logic levels, the associated bit should be programmed within the PIN_OR_1 register (pin override register) at address 0x0C. The logic values within the PIN_OR_1 register become active when the user sets the Pin Override Enable bit to HIGH within that same register. Table 1-2 shows: 1. The default logic state set by the internal pull-up or pull-down resistors. 2. The default values within the Pin Override register upon reset. More details are given in Section 4.15. Table 1-2: GS2986 Default Start-up Settings Name Description Default State set by Internal Resistors Default State within the Pin Override Register BYPASS Bypasses the reclocker stage when set HIGH. 0 0 AUTOBYPASS When set HIGH, this bit automatically bypasses the reclocker stage when the PLL is not locked to a supported rate. 00 AUTO/MAN When set HIGH, the standard is automatically detected from the input data rate. 10 SS0, SS1 When AUTO/MAN is set HIGH, SS[1:0] are outputs displaying the data rate to which the PLL has locked. Therefore, the bits will not have a default start-up value. None 0:0 KBB Controls the loop bandwidth of the PLL. Floating Ground DATA_MUTE Mutes the DDO0/DDO0 and DDO1/DDO1 (if data is selected) outputs when LOW. 10 DATA/CLOCK HIGH = DATA LOW = CLOCK 00 DE_EN De-emphasis on/off pin for serial digital output. HIGH = de-emphasis on LOW = de-emphasis off 00 |
类似零件编号 - GS2986 |
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类似说明 - GS2986 |
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