数据搜索系统,热门电子元器件搜索 |
|
TPD12S520DBTR 数据表(PDF) 11 Page - Texas Instruments |
|
|
TPD12S520DBTR 数据表(HTML) 11 Page - Texas Instruments |
11 / 22 page VIA to GND Plane VIA to 5V Plane VIA to 3.3V Plane VIA to LV Plane Pin to GND Legend TPD12S520 HDMI Connector 1 TPD12S520 www.ti.com SLVS640F – OCTOBER 2007 – REVISED FEBRUARY 2015 10 Layout 10.1 Layout Guidelines • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. • Route the protected traces as straight as possible. • Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. 10.2 Layout Example Figure 10. TPD12S520DBT Layout Example Use external and internal ground planes and stitch them together with VIAs as close to the GND pins of TPD12S520 as possible. This allows for a low impedance path to ground so that the device can properly dissipate an ESD event. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPD12S520 |
类似零件编号 - TPD12S520DBTR |
|
类似说明 - TPD12S520DBTR |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |