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MCP1700 数据表(PDF) 10 Page - Microchip Technology

部件名 MCP1700
功能描述  Low Quiescent Current LDO
Download  28 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP1700 数据表(HTML) 10 Page - Microchip Technology

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MCP1700
DS20001826C-page 10
 2005-2013 Microchip Technology Inc.
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
3.1
Ground Terminal (GND)
Regulator ground. Tie GND to the negative side of the
output and the negative side of the input capacitor.
Only the LDO bias current (1.6 µA typical) flows out of
this pin; there is no high current. The LDO output
regulation is referenced to this pin. Minimize voltage
drops between this pin and the negative side of the
load.
3.2
Regulated Output Voltage (VOUT)
Connect VOUT to the positive side of the load and the
positive terminal of the output capacitor. The positive
side of the output capacitor should be physically
located as close to the LDO VOUT pin as is practical.
The current flowing out of this pin is equal to the DC
load current.
3.3
Unregulated Input Voltage Pin
(VIN)
Connect VIN to the input unregulated source voltage.
As with all low dropout linear regulators, low source
impedance is necessary for the stable operation of the
LDO. The amount of capacitance required to ensure
low source impedance will depend on the proximity of
the input source capacitors or battery type. For most
applications, 1 µF of capacitance will ensure stable
operation of the LDO circuit. For applications that have
load currents below 100 mA, the input capacitance
requirement can be lowered. The type of capacitor
used
can
be
ceramic,
tantalum
or
aluminum
electrolytic. The low ESR characteristics of the ceramic
will yield better noise and PSRR performance at high
frequency.
3.4
No Connect (NC)
No internal connection. The pins marked NC are true
“No Connect” pins.
3.5
Exposed Thermal Pad (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the GND pin; they
must be connected to the same potential on the Printed
Circuit Board (PCB).
TABLE 3-1:
PIN FUNCTION TABLE
Pin No.
SOT-23
Pin No.
SOT-89
Pin No.
TO-92
Pin No.
2x2 DFN-6
Name
Function
1
1
1
3
GND
Ground Terminal
23
3
6
VOUT
Regulated Voltage Output
32
2
1
VIN
Unregulated Supply Voltage
2, 4, 5
NC
No Connect
7
EP
Exposed Thermal Pad


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