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TDA2HABRQAASQ1 数据表(PDF) 4 Page - Texas Instruments

部件名 TDA2HABRQAASQ1
功能描述  TDA2x ADAS Applications Processor 17mm Package (AAS Package) Silicon Revision 2.0
Download  380 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TDA2HABRQAASQ1 数据表(HTML) 4 Page - Texas Instruments

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TDA2HA-17, TDA2HG-17
SPRS952A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Submit Documentation Feedback
Product Folder Links: TDA2HA-17 TDA2HG-17
Table of Contents
Copyright © 2015–2016, Texas Instruments Incorporated
Table of Contents
1
Device Overview
......................................... 1
1.1
Features
.............................................. 1
1.2
Applications
........................................... 2
1.3
Description
............................................ 2
1.4
Functional Block Diagram
........................... 3
2
Revision History
......................................... 5
3
Device Comparison
..................................... 6
3.1
Device Comparison Table
............................ 6
3.2
Related Products
..................................... 8
4
Terminal Configuration and Functions
.............. 9
4.1
Terminal Assignment
................................. 9
4.2
Ball Characteristics
.................................. 10
4.3
Multiplexing Characteristics
......................... 65
4.4
Signal Descriptions
.................................. 80
5
Specifications
......................................... 116
5.1
Absolute Maximum Ratings
........................ 116
5.2
ESD Ratings
....................................... 117
5.3
Power on Hour (POH) Limits
...................... 117
5.4
Recommended Operating Conditions
............. 118
5.5
Operating Performance Points
..................... 121
5.6
Power Consumption Summary
.................... 136
5.7
Electrical Characteristics
........................... 136
5.8
Thermal Resistance Characteristics
............... 144
5.9
Power Supply Sequences
......................... 145
6
Clock Specifications
................................. 156
6.1
Input Clock Specifications
......................... 157
6.2
DPLLs, DLLs Specifications
....................... 165
7
Timing Requirements and Switching
Characteristics
........................................ 169
7.1
Timing Test Conditions
............................ 169
7.2
Interface Clock Specifications
..................... 169
7.3
Timing Parameters and Information
............... 169
7.4
Recommended Clock and Control Signal Transition
Behavior
............................................ 171
7.5
Virtual and Manual I/O Timing Modes
............. 171
7.6
Video Input Ports (VIP)
............................ 174
7.7
Display Subsystem – Video Output Ports
......... 187
7.8
Display Subsystem – High-Definition Multimedia
Interface (HDMI)
................................... 197
7.9
External Memory Interface (EMIF)
................. 197
7.10
General-Purpose Memory Controller (GPMC)
..... 197
7.11
Timers
.............................................. 220
7.12
Inter-Integrated Circuit Interface (I2C)
............. 220
7.13
Universal Asynchronous Receiver Transmitter
(UART)
............................................. 223
7.14
Multichannel Serial Peripheral Interface (MCSPI)
. 224
7.15
Quad Serial Peripheral Interface (QSPI)
.......... 230
7.16
Multichannel Audio Serial Port (McASP)
.......... 236
7.17
Universal Serial Bus (USB)
........................ 254
7.18
Peripheral Component Interconnect Express
(PCIe)
.............................................. 256
7.19
Controller Area Network Interface (DCAN)
........ 256
7.20
Ethernet Interface (GMAC_SW)
................... 257
7.21
eMMC/SD/SDIO
................................... 268
7.22
General-Purpose Interface (GPIO)
................ 284
7.23
System and Miscellaneous interfaces
............. 284
7.24
Test Interfaces
..................................... 284
8
Applications, Implementation, and Layout
...... 289
8.1
Introduction
........................................ 289
8.2
Power Optimizations
............................... 290
8.3
Core Power Domains
.............................. 304
8.4
Single-Ended Interfaces
........................... 315
8.5
Differential Interfaces
.............................. 317
8.6
Clock Routing Guidelines
.......................... 335
8.7
DDR2/DDR3 Board Design and Layout
Guidelines
.......................................... 337
9
Device and Documentation Support
.............. 372
9.1
Device Nomenclature & Orderable Information
.... 372
9.2
Tools and Software
................................ 374
9.3
Documentation Support
............................ 375
9.4
Receiving Notification of Documentation Updates
. 375
9.5
Related Links
...................................... 375
9.6
Community Resources
............................. 376
9.7
Trademarks
........................................ 376
9.8
Electrostatic Discharge Caution
................... 376
9.9
Export Control Notice
.............................. 376
9.10
Glossary
............................................ 376
10
Mechanical Packaging and Orderable
Information
............................................. 377
10.1
Mechanical Data
................................... 377


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